1. AIDA update Steve Thomas ASIC Design Group 9 December 2008

2. 9 / 12 / 2008AIDA update2 Digital design Place and route Pin positioning Analogue matching Threshold mismatch PORGAMRAYS result Simulation Time-scales Overview

3. 9 / 12 / 2008AIDA update3 Digital layout (test version) Full layout Bottom edge, with control register connections Signals for one channel, mostly grouped in pairs (differential mode to minimise substrate coupling)

4. 9 / 12 / 2008AIDA update4 Threshold mismatch Vth0 matching for PMOS ~15mV/sqrt(WL) Matching is important for low current mirrors, eg feedback circuit. Mismatch may be due to other factors, not included in the models (interface charge, for example). The correct model is essential for optimising low current circuits.

5. 9 / 12 / 2008AIDA update5 Process monitor results (PORGAMRAYS)

6. 9 / 12 / 2008AIDA update6 Subthreshold plot – varying V th0 V th0 variation causes constant threshold mismatch over all currents Range of V th0 is ~80mV, in order to cause factor of 10 difference in leakage

7. 9 / 12 / 2008AIDA update7 Subthreshold plot – varying C it C it variation causes large threshold mismatch at low current, but better matching at high current.

8. 9 / 12 / 2008AIDA update8 Statistical simulation – varying V th0 &C it Leakage / threshold plot, equivalent to process monitor results. Simulation can be extended for complete analogue channel

9. 9 / 12 / 2008AIDA update9 Time-scales Completion of top-level layout: December Final checking, design review: January (deadline 26 th ) Manufacture : Feb - April Testing : May – June Second iteration: start as soon as test results are available (beam tests not essential). Finalisation of second iteration definitely needs physics test results.