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Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1.

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Presentation on theme: "Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1."— Presentation transcript:

1 Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1

2 Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 2 q Is a 32-bit ALU as fast as a 1-bit ALU? q Is there more than one way to do addition?  Two extremes: ripple carry and sum-of-products c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 Problem: ripple carry adder is slow

3 Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 3 q An approach in-between our two extremes q More complexity (gates) vs less propagation (levels) q Motivation: q If we didn't know the value of carry-in, what could we do?  When would we always generate a carry? g i = a i b i  When would we propagate the carry? p i = a i + b i q Rewriting the carry equations, we get: c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 or c 2 = c 3 = g 2 + p 2 c 2 or c 3 = c 4 = g 3 + p 3 c 3 or c 4 = Carry-lookahead adder

4 Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 4 Carry-lookahead adder block q Consider the equation for the last carry c4: q c4 = g3 + (p3.g2) + (p3.p2.g1) + (p3.p2.p1.g0) + (p3.p2.p1.p0.c0), or …. q c4 = G0 + P0.c0, where G0 = g3 + (p3.g2) + (p3.p2.g1) + (p3.p2.p1.g0) P0 = p3.p2.p1.p0 q Calling c4 as C1 and c0 as C0, we have: C1 = G0 + P0.C0 C0 ALU0 CarryIn C1 P0 G0 a0 b0 a1 b1 a2 b2 a3 b3 P0 G0 C0 Result 0..3 1-bit Carry-lookahead unit (CLA)

5 Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 5 q Use 4-bit ALU and a 4-bit CLA building blocks q I.e., given Pi, Gi and C0, 4-bit CLA can find C1, C2, C3, C4 in parallel! q Ripple is eliminated ! q Ripple carry speed: q (16 hops between 1-bit ALUs) * (2 logic levels at each ALU) = 32 gate delays q CLA-adder speed: q (1 logic level to compute pi, gi) + (2 logic levels to compute Pi, Gi from pi,gi) + (2 logic levels at CLA to compute Ci) = 5 gate delays !! Use principle to build bigger adders CarryIn Result0--3 ALU0 CarryIn Result4--7 ALU1 CarryIn Result8--11 ALU2 CarryIn CarryOut Result12--15 ALU3 CarryIn C1 C2 C3 C4 P0 G0 P1 G1 P2 G2 P3 G3 pi gi pi + 1 gi + 1 ci + 1 ci + 2 ci + 3 ci + 4 pi + 2 gi + 2 pi + 3 gi + 3 a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 a11 b11 a12 b12 a13 b13 a14 b14 a15 b15 Carry-lookahead unit 4-bit


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