1. Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 5, 2012 Synchronous Circuits

2. Today Clocking –Latches –Registers Timing discipline Penn ESE370 Fall2012 -- DeHon 2

3. Accumulator Consider an accumulator based on your 16b adder: What can change the observed delay of this accumulator? Penn ESE370 Fall2012 -- DeHon 3

4. Challenge Logic paths have different delays –E.g. different output bits in an adder Delay of signal data dependent –E.g. length of carry Delay is chip dependent –E.g. Threshold Variation Delay is environment dependent –E.g. Temperature Penn ESE370 Fall2012 -- DeHon 4

5. Challenge Logic paths have different delays Delay of signal data dependent Delay is chip dependent Delay is environment dependent Proper behavior depends on inputs being coordinated –Match the inputs that should interact Penn ESE370 Fall2012 -- DeHon 5

6. Accumulator Consider an accumulator based on your 16b adder: What timing property must hold for this to function correctly? Penn ESE370 Fall2012 -- DeHon 6

7. Accumulator Why don’t we have to worry about: –Result coming out too early? (too fast?) –The accumulation bits change at different times? Penn ESE370 Fall2012 -- DeHon 7

8. Discipline Add circuit elements to –hold values –and change at coordinated point Control when changes seen by circuit Only have to make sure to wait long enough for all results Decouple –timing of signal change –from timing of signal usage Penn ESE370 Fall2012 -- DeHon 8

9. Register Use Where do we commonly use registers in our circuits? Penn ESE370 Fall2012 -- DeHon 9

10. Synchronous Discipline Add state elements (registers, latches) Compute –From state elements –Through combinational logic –To new values for state elements Penn ESE370 Fall2012 -- DeHon 10

11. What does this do? Penn ESE370 Fall2012 -- DeHon 11

12. Latch  =0  Out=In  =1  Out=Out  transitions 0  1 Out holds value Penn ESE370 Fall2012 -- DeHon 12

13. Latch In pass-through mode (  =0), –acts like buffer In latch mode (  =1), –holds last value given Penn ESE370 Fall2012 -- DeHon 13

14. Latch In pass-through mode (  =0), –acts like buffer In latch mode (  =1), –holds last value given Ideally: on 0  1 transition of  snapshots value Penn ESE370 Fall2012 -- DeHon 14

15. Latch In pass-through mode (  =0), –acts like buffer In latch mode (  =1), –holds last value given Ideally: on 0  1 transition of  snapshots value What timing relations must hold between In and  for this behavior to occur? Penn ESE370 Fall2012 -- DeHon 15

16. Latch Timing Ideally: on 0  1 transition of  snapshots value What timing relations must hold between In and  for this behavior to occur? Can  transition simultaneous with In? Can In transition slightly before  ? Can In transition slightly after  ? Penn ESE370 Fall2012 -- DeHon 16

17.  =0 In=0 Node values? Penn ESE370 Fall2012 -- DeHon 17

18. T=0 both transition to 1  =0  1 In=0  1 Node waveforms (preclass 2) Penn ESE370 Fall2012 -- DeHon 18

19. In transitions  after  ?  =0  1 In=0  1 What happens to waveform? Penn ESE370 Fall2012 -- DeHon 19

20. In transitions  before  ?  =0  1 In=0  1 What happens to waveform? Penn ESE370 Fall2012 -- DeHon 20

21. Latch Timing Must present input value sufficiently before the  transitions 0  1 –Must have time to propagate and charge Out –About how long is that in this case? Setup Time (t su ) – must setup latch input prior to pass  hold transition Penn ESE370 Fall2012 -- DeHon 21

22. Latch Timing Must not change input before switched over to hold state –How long in this case? –Takes time for inverter to charge before hold path enabled. Penn ESE370 Fall2012 -- DeHon 22

23. Latch Timing Must not change input before switched over to hold state Hold Time (t hold )– must hold data input until pass  hold transition complete Penn ESE370 Fall2012 -- DeHon 23

24. What happens here? Penn ESE370 Fall2012 -- DeHon 24

25. Observe Latch alone –In flow-through mode half of cycle –Can still get flow-through, combinational cycles Penn ESE370 Fall2012 -- DeHon 25

26. Multiple Latch Discipline Open latches at disjoint times At all times: one latch on every path is closed Penn ESE370 Fall2012 -- DeHon 26

27. Register Two back-to-back latches –Open one latch at a time –Having one of each on every cycle breaks up combinational cycle Penn ESE370 Fall2012 -- DeHon 27

28. Register Pass  hold on input latch samples value Hold  pass on output latch presents stored value to circuit Penn ESE370 Fall2012 -- DeHon 28 Master and Slave latches

29. Register How long from  1 fall to output? –Part of clk  output (t clk-q ) Penn ESE370 Fall2012 -- DeHon 29

30. What does this do? Penn ESE370 Fall2012 -- DeHon 30

31. What does this do? Outputs when –Input 0? –Input 1? Can ever both be low? What does output waveform look like? Penn ESE370 Fall2012 -- DeHon 31

32. Clocking Discipline Penn ESE370 Fall2012 -- DeHon 32 Identify: setup, hold, clk->Q, logic evaluation

33. Clocking Discipline Penn ESE370 Fall2012 -- DeHon 33

34. Clocking Discipline Follow discipline of combinational logic broken by registers Compute –From state elements –Through combinational logic –To new values for state elements As long as clock cycle long enough, –Will get correct behavior Penn ESE370 Fall2012 -- DeHon 34

35. Ideas Synchronize circuits –to external events –disciplined reuse of circuitry Leads to clocked circuit discipline –Uses state holding element –Prevents Combinational loops Timing assumptions (More) complex reasoning about all possible timings Penn ESE370 Fall2012 -- DeHon 35

36. Admin Udit Office Hours Today  Review Exam Wednesday –No class at noon –Exam 7—9pm in Moore 216 Lecture on Friday Informal talk on Tabula –Friday 1:30pm, Moore 315 (IC Lab) Penn ESE370 Fall2012 -- DeHon 36