1. 1 Memory Test - Debugging Test Vectors Without ATE Steve Westfall Director Visual Testbench Engineering Summit Design Inc.

2. 2 Why Do This? Introduces Concurrent Engineering into the process Allows for Off-line Test Program development Improves Test Program Debug efficiency

3. 3 Outline Introduction The Device Model The ATE Model ATE Model Functionality Debugging The Test Program Adding Memory Test Features Edge Related Tests Implementation Notes Conclusion

4. 4 Introduction Goals Testbench Methodology What is not covered

5. 5 Goals Debug functional vectors allowing for compression constructs Debug the timing used to test the device Debug edge related tests

6. 6 Testbench Methodology Functionality is defined by: –Timing Diagrams –Sequence of Timing Diagrams Reactive Testbench –Applies timing according to external control –Timing is applied by calling a function to fetch and apply the Timing Diagram

7. 7 Reactive Testbench - Example Timing Diagrams: read, write, wait, ack Control is: 00apply read 01apply write 10apply wait 11apply ack Testbench becomes: switch( control ) { case 00: applyTiming( read ); break; case 01: applyTiming( write ); break; case 10: applyTiming( wait ); break; case 11: applyTiming( ack ); break; }

8. 8 What is not covered ATE Analog Characteristics Device Analog Characteristics DUT Board Analog Characteristics

9. 9 The Device Model Accurate Time HDL Model is Assumed Model may be Behavioral, RTL or Gate Level –NOTE: Behavioral or RTL may need modifications for Accurate Timing Behavioral/RTL are usually unit delay –Scale to Accurate Time if possible –Simulates Faster

10. 10 The ATE Model A reactive Testbench forms the Model ATE Rules Checking gives ATE behavior –Edge Rules (pulse width, cycle boundary) –Inter Cycle Edge Rules –Compression Construct Rules –Valid Shape and Format Rules Table Driven Rules Database Access for Timing Diagrams

11. 11 Simulation Model HDL ATE Model Simulation Environment HDL Device Model SignalConnections Test Program Control ATE Rules Simulation Report

12. 12 ATE Model Functionality There are many Differences between Simulation and ATE Waveforms A Translation Unit Addresses the Differences Timing Diagrams obtained from a Database ATE Rules checked in several logical blocks The model is parametric with respect to pins DUT Model allows for ATE to Device Mapping

13. 13 ATE Model DUT Pins DUT Board Parametric Generic HDL ATE Model Translation Unit Translation Unit Parametric ATE Pins Program Control Report File ATE Shapes ATE Compression Rules ATE Timing Rules

14. 14 Debugging The Test Program The system is data driven –Edges, Shapes and Vectors can be changed On-the-fly Simulation results are viewed as Waveforms A Report File is the key to easy debug –Allows for postmortem debug –Breakpoints in reporting allows for detail at runtime

15. 15 Adding Memory Test Features Memory Test is ALPG oriented Standard Algorithms are Implemented in the Model Control Program becomes a sequence of algorithm selections Vector Set Needs Saving if ATE is not ALPG

16. 16 Algorithm Block Control Program Control Program Walking Ones Walking Ones Checker Board Checker Board Adjacent Cell Adjacent Cell Timing Sequence Timing Sequence Vector Output Vector Output Algorithm Selection Algorithm Selection... ATE Vectors ATE Timing Algorithm Select

17. 17 Edge Related Tests Involves two components in Control Program –Requires Looping –Requires increment of edge time Use the HDL and parameterize requirements Loop requirements are simple Edge time requirements are more involved –Signal Name to move is symbolic –Edge parameters are parametric

18. 18 Implementation Notes HDL is used when a simple scanner could not Control File kept as a scannable file “C” was used form most internal work –Apply Timing –Rules –Algorithms Some ATE Rules get “bent” to cover Design –Ambiguous I/O Transitions for example

19. 19 Conclusion A Reactive Testbench is used to Model ATE ATE Rules gives a Behavioral ATE Model Debug is accomplished by Error Message Standard Algorithms are added for ALPG Edge Related tests are allowed for timing Functional Vectors are validated without ATE