1. MAPS ECAL Nigel Watson Birmingham University  Technical Status  Future Plans  Summary For the CALICE MAPS group J.P.Crooks, M.M.Stanitzki, K.D.Stefanov, R.Turchetta, M.Tyndel, E.G.Villani (STFC-RAL) J.A.Ballin, P.D.Dauncey, A.-M.Magnan, M.Noy (Imperial) Y.Mikami, O.D.Miller, V.Rajovic, NKW, J.A.Wilson (Birmingham) SiD Workshop RAL 14-16 Apr 2008

2. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20082 MAPS ECAL: basic concept How small? EM shower core density at 500GeV is ~100/mm 2 Pixels must be<100  100  m 2 Our baseline is 50  50  m 2 Gives ~10 12 pixels for ECAL – “Tera-pixel APS” How small? EM shower core density at 500GeV is ~100/mm 2 Pixels must be<100  100  m 2 Our baseline is 50  50  m 2 Gives ~10 12 pixels for ECAL – “Tera-pixel APS” Swap ~0.5x0.5 cm 2 Si pads with small pixels “Small” := at most one particle/pixel 1-bit ADC/pixel, i.e. Digital ECAL Effect of pixel size 50  m 100  m >1 particle/ pixel Incoming photon energy (GeV) Weighted no. pixels/event

3. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20083 New since Jan. workshop?  What is it sensible to show?  Results from testbeam??  Hints that we are starting to understand what is going on?  JB evt display? Layer-layer correlation plots a la TM?  Etc?

4. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20084 CALICE INMAPS TPAC1 Architecture-specific analogue circuitry 4 diodes Ø 1.8  m First round, four architectures/chip (common comparator+readout logic) INMAPS process: deep p-well implant 1 μm thick under electronics n-well, improves charge collection 0.18  m feature size

5. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20085 The CALICE TPAC1  50x50  m cell size  Comparator per pixel  Capability to mask individual pixels  4 Diodes for ~uniform response w.r.t threshold  13 bit time stamp (>8k bunches individually tagged)  Hit buffering for entire bunch train (~ILC occupancy)  Threshold adjustment for each pixel  Usage of INMAPS (deep-p well) process [Marcel Stanitzki]

6. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20086 8.2 million transistors 28224 pixels; 50 microns; 4 variants Sensitive area 79.4mm 2 Four columns of logic + SRAM  Logic columns serve 42 pixels  Record hit locations & timestamps  Local SRAM  11% deadspace due to readout/logic Data readout  Slow (<5 MHz)  Current sense amplifiers  Column multiplex  30 bit parallel data output TPAC1 overview “region” “Group” (region=7 groups of 6 pixels)

7. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20087 Attention to detail 2: beam background  Beam-beam interaction by GUINEAPIG  LDC01sc (Mokka)  2 machine scenarios studied :  500 GeV baseline,  1 TeV high luminosity purple = innermost endcap radius 500 ns reset time  ~ 2‰ inactive pixels [O.Miller] Study to be repeated in SiD01 Verify optimisation Study to be repeated in SiD01 Verify optimisation X (mm) y (mm)

8. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20088 Progress with sensor tests Work ongoing to test unformity of threshold and gain Report today on testbeam

9. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-20089 SiD 16mm 2 area cells ZOOM 50  50 μm 2 MAPS pixels Tracking calorimeter

10. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200810 Physics simulation 0.5 GeV MPV = 3.4 keV σ = 0.8 keV 5 GeV MPV = 3.4 keV σ = 0.8 keV 200 GeV MPV = 3.4 keV σ = 0.8 keV Geant4 energy of simulated hits E hit (keV)  MAPS geometry implemented in Geant4 detector model (Mokka) for LDC detector concept  Peak of MIP Landau stable with energy  Definition of energy: E  N pixels  Artefact of MIPS crossing boundaries  Correct by clustering algorithm  Optimal threshold (and uniformity/stability) important for binary readout Threshold (keV)  (E)/E 20 GeV photons

11. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200811 Hit buffering for train

12. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200812  Physics data rate low – noise dominates  Optimised diode for  Signal over noise ratio  Worst case scenario charge collection  Collection time Device level simulation Signal/noise 0.9 μm 1.8 μm 3.6 μm Distance to diode (charge injection point) Signal/Noise

13. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200813 Attention to detail 1: digitisation [J.Ballin/A-M.Magnan] Digital ECAL, essential to simulate charge diffusion, noise, in G4 simulations

14. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200814 TestingTesting  Tested device-level simulations using laser-based charge diffusion measurements at RAL   1064, 532,355 nm,focusing < 2 μm, pulse 4ns, 50 Hz repetition, fully automated  Cosmics and source setup, Birmingham and Imperial, respectively.  Beam test at DESY, 10-17 Dec. 2007  Analysis in progress  Expand work on physics simulations  Test performance of MAPS ECAL in ILD and SiD detector concepts  Emphasis on re-optimisation of particle flow algorithms  Cannot be done without specific, detailed simulation models... July: 1 st sensors delivered to RAL July: 1 st sensors delivered to RAL

15. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200815 2 pixels with analog output (A & B) 1 Pixel not active & read out (C) Used for  Measurement of charge spread  Cross-check device simulations  Analog front-end testing  Gain calibration (to be done) All results are PRELIMINARY A B C [Marcel Stanitzki] Analogue test pixels

16. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200816 A B C Area scanned by Laser Same design, but no deep p-well [Marcel Stanitzki] Without deep p-well

17. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200817 A B C Area scanned by Laser [Marcel Stanitzki] With deep p-well: I

18. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200818 Pixel APixel B [Marcel Stanitzki] With deep p-well: II

19. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200819  A Tera-Pixel ECAL is challenging  Benefits  No readout chips  CMOS is well-known and readily available  Ability to make thin layers  Current sources of concern  DAQ needs  Power consumption/Cooling System considerations

20. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200820 DAQ requirements  O(10 12 ) channels are a lot...  Physics rate is not the limiting factor  Beam background and Noise will dominate  Assuming 2625 bunches and 32 bits per Hit  10 6 Noise hits per bunch  ~O(1000) Hits from Beam background per bunch (estimated from GuineaPIG)  Per bunch train  ~80 Gigabit / 10 Gigabyte  Readout speed required 400 Gigabit/s  CDF SVX-II can do 144 Gigabit/s already

21. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200821 Cooling and power  Cooling for the ECAL is a general issue  Power Savings due to Duty Cycle (1%)  Target Value for existing ECAL ASICS  4 µW/mm2  Current Consumption of MAPS ECAL:  40 µW/mm2 depending on pixel architecture  TPAC1 not optimized at all for power consumption  Compared to analog pad ECAL  Factor 1000 more Channels  Factor 10 more power  Advantage: Heat load is spread evenly

22. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200822 [Marcel Stanitzki] Thermal properties

23. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200823 MAPS testbeam  Desy 10-17 Dec. 2007  Extremely tight schedule…  4 sensors, PMT coincidence trigger  3, 6 GeV e -  With/without tungsten pre-shower material  Threshold scans  USB_DAQ

24. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200824

25. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200825

26. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200826 PMT trigger

27. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200827 Sensor setup in testbeam

28. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200828

29. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200829 Concentrate on shapers

30. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200830 StrategyStrategy  Want to start with the highest purity sample we can  Scintillators behaviour “not optimal”  Ensure sensor hits genuine  Use clusters of hits initially, not single pixels  Can we match clusters between sensors?

31. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200831 ClusteringClustering

32. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200832 Layer-layer correlations: x

33. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200833 Layer-layer correlations: y

34. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200834 Layer-layer alignment

35. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200835 …and funding  Recognised as generic technology  Much interest to continue development of concept for ECAL  Including for SiD  …

36. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200836 MAPS summary  Concept of CMOS MAPS digital ECAL for ILC  Multi-vendors, cost/performance gains  New INMAPS deep p-well process (optimise charge collection)  Four architectures for sensor on first chips, delivered to RAL Jul 2007  Tests of sensor performance in progress: sources, charge diffusion, cosmics, testbeam  Physics benchmark studies, compare MAPS vs. analogue Si-W designs  In framework of SiD and IDC detector concepts

37. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200837 SummarySummary  MAPS ECAL: alternative to baseline design (analogue SiW)  Multi-vendors, cost/performance gains  New INMAPS deep p-well process (optimise charge collection)  Four architectures for sensor on first chips  Tests of sensor performance ongoing  Physics benchmark studies with MAPS ECAL to evaluate performance relative to standard analogue Si-W designs, for both SiD (and ILD) detector concepts  Future plans  Systematic studies of pixel to pixel gain and threshold variations  Absolute gain calibration  Second sensor…

38. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200838 Backup slides…

39. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200839 The sensor test setup 5 dead pixels for logic : -hits buffering (SRAM) - time stamp = BX (13 bits) - only part with clock lines. 84 pixels 42 pixels Data format 3 + 6 + 13 + 9 = 31 bits per hit 7 * 6 bits pattern per row Row index 1*1 cm² in total 2 capacitor arrangements 2 architectures 6 million transistors, 28224 pixels

40. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200840 Architectures on ASIC1 PresamplerPreshaper Type dependant area: capacitors, and big resistor or monostable

41. Nigel Watson / BirminghamSiD Workshop, RAL, 15-Apr-200841  Physics data rate low – noise dominates  Optimised diode for  Signal over noise ratio  Worst case scenario charge collection  Collection time. Device level simulation Using Centaurus TCAD for sensor simulation + CADENCE GDS file for pixel description Signal/noiseCollected charge 0.9 μm 1.8 μm 3.6 μm Distance to diode