1. Contemporary DRAM memories and optimization of their usage Nebojša Milenković and Vladimir Stanković, Faculty of Electronic Engineering, Niš

2. Theme’s importance Dynamic RAM (DRAM) memories have been a primary choice for implementing main memories for many years. This qualify them as a candidate for study in course on Computer organization, which take all students in Computer science department on our faculty. This presentation asumes that students already know the basic facts of conventional (asynchronous) DRAM memory.

3. DRAM’s access phases All DRAM accesses have at least three common phases through which the memory array must proceed. These phases are precharge, row access and column access.

4. DRAM parameters The two main parameters that differentiate DRAM devices are the latency and the bandwidth: latency- the number of clock cycles that elapse between a request for data and the arrival of the first line of the requested data at the requester input pins; bandwidth-the rate at which the subsequent data lines are returned after the first line arrives

5. Fast Page Mode DRAM Contemporary implementation of conventional DRAMs use sens amplifiers as a buffer of open row, in which data can be accessed for shorter time than if data is in memory array. Such DRAMs are known as Fast Page Mode DRAMs (FPM DRAM ).

6. Improving DRAM architecture A few years ago begun significant changes to DRAM architecture in an attempt to improve both the bandwidth and the latency of the main memory system. Most of these approaches use conventional DRAM cores but take advantage of the large amount of data available on the sense amplifiers during an access to dramatically improve bandwidth on and off the memory device.

7. Examples of new DRAM architectures Examples include among others: Direct Rambus architecture, Double Date Rate SDRAM-DDR SDRAM, and SRAM added to the DRAM device:  Virtual Channel SDRAM - VCSDRAM,  Enhanced SDRAM - ESDRAM, and  Cached DRAM - CDRAM). The speed of the DRAM core is also being improved, but not at the rate of the processor core.

8. Widely used types of DRAM In this presentation we will limit only on SDR SDRAM, DDR SDRAM and DR DRAM architecture. The reason for this is their wide usage in comercial computers today and chance for them to retain leading position in the near future.

9. Synchronous DRAM (SDRAM) Important step in developing DRAM architecture was introducing synchronous interface, such that the SDRAM latches information to and from controller based on a clock signal. SDRAM is controlled with comands, which are combination of logic levels of control signals.

10. Synchronous DRAM SDRAM devices typically have a programmable register that holds a bytes per-request value. SDRAM may therefore return many bytes over several cycles per request. The advantages include the elimination of the timing strobes and the availability of data from the DRAM each clock cycle. Comparing the access time of SDRAM with that of the conventional DRAM, the burst access time of SDRAM is much faster than that of the conventional DRAM while there is not much difference in the random access time.

11. SDR and DDR SDRAM SDRAM apears in two variants: as Single Data Rate (SDR SDRAM) and Double Date Rate (DDR SDRAM). They differ in that SDR SDRAM transmits one word per clock cycle, while DDR SDRAM transmits two words per clock cycle, each one on rising and falling edge of clock signal.

12. Several banks in a SDRAM chips The memory chip is separated into several banks, so that controls can be performed by the bank. A row buffer is asociated with every bank. This enable concurent operation of diferrent banks. This results in increasing bandwidth of memory chip.

13. DirectRambus DRAM (DRDRAM) DRDRAM obtains high bandwidth from a single DRAM device using aggressive signaling technology. Data are transferred across a 16-bit data bus on both edges of a 400 MHz clock, providing a pick transfer rate of 1.6 Gbytes per second. DRDRAMs employ two techniques to maximize actual transfer rate that can be sustained on the data bus. 1.Each DRDRAM device has multiple banks, allowing pipelining and interleaving of accesses to different banks, 2.Commands are sent to DRAM devices over two independent control buses. Splitting the control buses allows the memory controller to send comands to independet banks concurrently.

14. Recent DRDRAMs The recent Rambus devices are 256 Mbit, and have 32 banks of 1 Mbyte each with 33 half-row buffers. Each half-row buffer is shared between adjacent banks, which implies that adjacent banks cannot be active simultaneously. The smallest addressable unit in a row is dualoct, which is 16 bytes.

15. Open/closed row policies Open-row policies hold the most recently accessed row in the row buffer. If the next request falls within that row, than only column access is needed. If a row buffer miss occurs, then the full row access is needed, including precharge. Open row policy is better for access patterns with high spatial locality. Closed-page policies, which are better for access patterns with little spatial locality, release the row buffer after an access, requiring only the ACT- RD/WR sequence upon the next access.

16. Optimization of average latency Minimum of average access time obtains with greatest number of accesses into already open rows of memory, present in buffers of active banks. Depending on locality of memory accesses in each program, data placement may be optimized with increase of hit to open rows in mind. This can be made by solutions which place nearly used data in consecutive memory locations.

17. Optimization with address remapping One solution which is not based on program features, uses the fact that most of computer configurations contain cache memories (in one or more levels), through which processor communicates with main memory. Data in DRAMs (banks, rows, columns) can be allocated so that data which map into the same set of cache blocks are placed into different banks. This can be made by XOR operation New bank index = (bank index) XOR (lower part of cache tag)

18. Permutation-based page interleaving scheme Such address remaping which reduce row buffer conflicts is known as a permutation-based page interleaving scheme.