1. Speaker: Utku Özcan ASIC Designer, R&D, Netaş, Turkey Designers: Utku Özcan,ASIC Designer İsmail Hakkı Topçu, Hardware Designer Ömer Aydın, Senior System Engineer {ozcan, topcu, aydin}@netas.com.tr A Novel Parametric ATM Adaptation Layer 1 Bridging Between PCM and ATM

2. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM ATM (Asynchronous Transfer Mode): A most recent network technology - voice, image and data transfer on the same network - support of users with different features - support high transfer rates between end users ATM network ATM (Asynchronous Transfer Mode)

3. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM User information is carried in 53 byte packets called ATM cells on an ATM network - user information acquired in 53 byte packets On the Transmitter - packets reassembled and sent to users On the Receiver ATM (Asynchronous Transfer Mode)

4. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM ATM Cell ATM cell payload (47 bytes) AAL1 Header (1 byte) ATM Header (5 bytes) Network element

5. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM End users described by QoS (Quality of Service) On ATM Users tell the network what kind of transfer will exist Network will be programmed for best performance according to this set of information QoS 1 QoS 2 Preparation of ATM to the users

6. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM ATM Network General Architecture Physical Layer (PHY) ATM Layer (ATM) AAL Layer (AAL) Physical Layer (PHY) ATM Layer (ATM) AAL Layer (AAL) AAL user An ATM network is implemented mostly as hardware AAL users are implemented mostly as software

7. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Basic QoS types CBR (Constant Bit Rate) VBR (Variable Bit Rate) Some of QoS data carried in ATM Header GFCVPI VCI PTI CLP HEC AAL1 Header ATM cell payload byte 1... ATM cell payload byte 2 ATM cell payload byte 47 0347 QoS List ATM QoS types

8. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM AAL ATM Adaptation Layer It serves as an interface between the users and the ATM network 5 different types of AAL are defined in ITU-T Standarts Most common AAL1 types AAL1: used in CBR type QoS (e.g. POTS) AAL5: used in VBR type QoS (e.g. Internet) AAL1AAL5 ATM Adaptation Layer

9. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM AAL1 ATM Adaptation Layer 1 - a connection based layer protocol - support to conventional phone networks - numerous researches on AAL1 - realtime voice or image transmission - ISDN network on ATM network ATM Adaptation Layer 1 (AAL1)

10. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM ISDN facility on ATM Physical Layer (PHY) ATM Layer (ATM) AAL Layer (AAL) ISDN Terminal Physical Layer (PHY) ATM Layer (ATM) AAL Layer (AAL) ISDN Terminal Support of 64 kbps voice traffic: ISDN over ATM Result: ISDN uses ATM advantages

11. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM ISDN Rate Adaption and AAL1 ISDN supports users with 64 kbps rate Today, most users have a bandwidth of lower than 64 kbps Rate adaption necessity: ITU-T X.30/V.110 standards All state-of-the-art AAL1 applications support new systems Support of old systems: X.30/V.110 feature in AAL1 Conventional AAL1 ?

12. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM NETAAL1: Netaş’ AAL1 Solution NETAAL1 Netaş AAL1 Solution - support to every kind of user - ISDN compatibility - user variety taking advantage of ATM Our AAL1

13. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM General Architecture of AAL1 AAL1 user data Convergence Sublayer Segmentation & Reassembly sublayer AAL1 PDU (48 bytes) AAL1 user data AAL1 PDU (48 bytes) ATM Layer AAL1 Header Calculator... CSI output SC Output 47 bytes 1 bit3 bits 1 byte... AAL1 Header Correction-Detection CSI Analysis SC Analysis 1 bit3 bits 1 byte 47 bytes Transmitter side Receiver side

14. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Main Functions of AAL1 Convergence Sublayer, CS Transmitter Side: - acquires user data in 47 byte packets - assigns a Sequence Count, SC for every 47 byte packet - prepares Convergence Sublayer Indication (CSI) Receiver Side: - sends 47 byte packets to the user - analyzes the sequence of 47 byte packets - analyzes timing information (CSI) Segmentation and Reassembly sublayer, SAR Transmitter Side: generates AAL1 packet from SC, CSI and 47 byte packets and sends it Receiver Side: - divides AAL1 packet into SC, CSI and 47byte packets

15. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM NETAAL1 General Configuration 4 x 2.048 Mbps PCM Bus 10 Mbps ATMBus Transmit Pointer RAM Transmit Payload RAM Receive Pointer RAM Receive Payload RAM NETAAL1 CPU

16. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Transmit side of NETAAL1 Transmit PCM Bus Transmit Parametric Algorithm Transmit Static Parameter Table CPU Transmit Dynamic Parameter Table Transmit Pointer RAM Transmit Payload RAM address data address data Transmit Payload Flag RAM Transmit SAR Scheduler Unit AAL1 Header Generator Transmit ATM Bus Interface Transmit ATM Bus CSSAR

17. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Transmit NETAAL1 CS Nth channel timeslot PCM Frame (125 μs.) Nth channel timeslot PCM Frame (125 μs.)... Mth X.30/V.110 FrameM+1th X.30/V.110 Frame Transmit Pointer Table bytebitFlag byte bitAAL1 Header ATM Header Payload Location for the Nth channel on the Transmit Side (in Payload RAM) 30th bit of X.30/V.110 frame Pointer Group for M+1th X.30/V.110 frame (80 Pointers) time

18. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Transmit NETAAL1 SAR Payload Flag RAM Payload Ready Transmit SAR Scheduler Unit address data SC RAM Payload Flag of Nth channel Transmit Payload RAM AAL1 Header Generator ATM Bus Interface ATM Bus N = N + 1 Nth Channel Payload Ready? Prepare AAL1 Header of Nth Channel Send Payload of Nth Channel to ATM Bus Interface SC = SC + 1

19. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Receive Side of NETAAL1 Receive ATM Bus Interface Receive Look Up Table Receive SNP/SN Analyzer Receive ATM Bus Receive Payload Flag RAM Receive Payload RAM Receive Parametric Algorithm Receive Pointer Table Receive Static Parameter Table CPU Receive Dynamic Parameter Table Receive PCM Bus data address SARCS

20. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Receive NETAAL1 SAR ATM Bus Interface ATM Bus VPIVCI Receive Look Up Table Nth address AAL1 Header SNP Error Detection- Correction AAL1 Header SN Analyzer ATM Cell Filter Receive Payload RAM Receive Payload Flag RAM Payload Ready Payload Flag of Nth Channel

21. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Receive NETAAL1 CS Nth channel timeslot PCM Frame (125 μs.) Nth channel timeslot PCM Frame (125 μs.)... Mth X.30/V.110 FrameM+1th X.30/V.110 Frame Receive Pointer Table bytebitFlag byte bitAAL1 Header ATM Header Payload Location for the Nth channel on the Receive Side (in Payload RAM) 30th bit of X.30/V.110 frame Pointer Group for M+1th X.30/V.110 frame (80 Pointers) time

22. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Design Technology NETAAL1 implemented as a digital integrated circuit designed with Verilog Hardware Description Language (Verilog HDL) 100.000 lines of Verilog and C code in 5 months always @(posedge clock) begin out_reg <= in_reg; end in_reg clock out_reg Flip-Flop Model FF

23. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Minimal CPU time statistics of postroute simulations for 4 cell transmission of the Transmit AAL1 Static Timing Analysis is mandatory for this complexity Design Environment Statistics

24. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Design Environment Statistics Parametric synthesis results of Transmit NETAAL1

25. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Design Environment Statistics Placement&Routing statistics of Transmit NETAAL1: Sept 1st - 30th, 1999

26. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Design Environment Statistics Parametric synthesis results of Receive NETAAL1

27. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Design Environment Statistics Placement&Routing statistics of Receive NETAAL1: Sept 1st - 10th, 1999

28. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM NETAAL1 has been implemented with Top-Down Design Flow Design Entry Synthesis P&R always @(posedge clock) out_reg <= in_reg; Verify comparison Automated verification environment chip Design Technology out_regin_reg clock

29. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Design Technology Transmit NETAAL1 Receive NETAAL1 CPU Simulation Model PCM Bus Simulation Model ATM Bus Simulation Model RAM Simulation Models open_aal1_connection (,,,, ); Internal monitors & cell file dumpers Testvector generators C Interfaces to external tools Verilog and C based Automated Verification Environment Macro Behavioral Model Generators Simulation mode check

30. Utku Özcan 3/11/1999 ICSPAT’99 A Novel Parametric AAL1 Bridging Between PCM and ATM Transmit NETAAL1 implemented in XC40150XV Receive NETAAL1 implemented in XC40150XV NETAAL1 implemented in Field Programmable Gate Arrays (FPGA) of Xilinx transistor count ca. 1.000.000 Design Technology