1. CPUMemoryIO-1IO-2 Address BUS Data BUS Control BUS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Memory Map 01230123 IO Map 8bytes 2bytes IO-1 IO-2 A3~A0 D7~D0 A3~A0 A1~A0 기본개념

2. CPUIO-1 A1 A0 /IORQ /CS control data D7 D6 D5 D4 D3 D2 D1 D0 R/W A1 A0 unsigned char *port; port = (unsigned char *)0x0; *port = 0x12; 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0001001000010010 00010010 0 0 Address Decoder /IO1_CS Control Register Write

3. CPUIO-1 A1 A0 /IORQ /CS control data D7 D6 D5 D4 D3 D2 D1 D0 R/W A1 A0 unsigned char *port; unsigned char data; port = (unsigned char *)0x1; Data = *port; 1 0 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1010111110101111 00010010 1 1 10101111 Address Decoder /IO1_CS Data Register Read Address Decoder 는 1)Logic Gate 로 구현 2)Nx2N Decoder 로 구현 3)PAL 이나 CPLD 로 구현

4. void port_init(void) { unsigned char *port; port =(unsigned char *) 0x03; *(port) = 0x90; // PA input, PB output, PC output } unsigned char getData_DIP(void) { unsigned char *port, data; port =(unsigned char *)0x00; data = *(port); return data; } main() { unsigned char DIP_data; port_init(); DIP_data = getData_DIP(); printf(“%0x”,DIP_data);// 10010111 이므로 97 출력 } D7D6D5D4D3D2D1D0 1 0 0 1 0 0 0 0 Mode 0 PA Input PC(up) Output PC(low) Output PB Output 강의노트 입력장치 인터페이스 Control Register

5. void port_init(void) { unsigned char *port; port =(unsigned char *) 0x03; *(port) = 0x80; // PA input, PB output, PC output } void set_LED(unsigned char data) { unsigned char *port; port =(unsigned char *)0x00; *(port) = data; } main() { port_init(); set_LED(0x0F); } D7D6D5D4D3D2D1D0 1 0 0 0 0 0 0 0 Mode 0 PA Output PC(up) Output PC(low) Output PB Output 강의노트 출력장치 인터페이스 1111000011110000 1111000011110000 Control Register

6. void port_init(void) { unsigned char *port; port =(unsigned char *) 0x03; *(port) = 0x80; // PA input, PB output, PC output } void set_LED(unsigned char data) { unsigned char *port; port =(unsigned char *)0x00; *(port) = data; } main() { port_init(); set_LED(0x3F); // 7-segment 에 0 이 표시됨 } D7D6D5D4D3D2D1D0 1 0 0 0 0 0 0 0 Mode 0 PA Output PC(up) Output PC(low) Output PB Output 강의노트 출력장치 인터페이스 Control Register

7. 8051 실습보드 P0[7:0], P2[7:0], ALE, /WR, /RD AD[7:0], A[15:8], ALE, /WR, /RD Character LCD PORTA[7:0] D0 D1 D2 D3 D4 D5 D6 D7 CPLD LCD_EN LCD_RS LCD_RW E RS R/W CPLD Logic (Verilog HDL) void clearscreen_lcd(void) { xdata unsigned char *pcode; // for External Memory pcode =(unsigned char xdata *)0xF000; *(pcode) = 0x00;// LCD_RS = 0; pcode = (unsigned char xdata *)0xF300; *(pcode) = CLEAR_DISPLAY; pcode = (unsigned char xdata *)0xF100; *(pcode) = 0x01;// LCD_EN = 1; *(pcode) = 0x00;// LCD_EN = 0; } Address (A0) RS(address) R/W E Valid Data 140nS D0-D7 void PutChar(unsigned char c) { pcode = (unsigned char xdata *)0xF000; *(pcode) = 0x01;// LCD_RS = 1; pcode = (unsigned char xdata *)0xF300; *(pcode) = c; pcode = (unsigned char xdata *)0xF100; *(pcode) = 0x01;// LCD_EN = 1; *(pcode) = 0x00;// LCD_EN = 0; }

8. 8051 P0[7:0], P2[7:0] AD[7:0], A[15:8] Character LCD PORTA[7:0] D0 D1 D2 D3 D4 D5 D6 D7 CPLD LCD_EN (LCD_CON[1]) LCD_RS (LCD_CON[2]) LCD_RW (LCD_CON[0]) E RS R/W Address (A0) RS(address) R/W E Valid Data 140nS D0-D7 P0[0] P0[7:0] if(A[15:8] == 8’hF3) P0[7:0] 은 AD[7:0] 과 같음 P2[7:0] 은 A[15:8] 과 같음