1. Click to edit Master title style Analysis and Modeling of Neural-Recording ADC Mentors: Wolfgang Eberle Vito Giannini Progress Update : Summer Internship Vaibhav Karkare

2. 2 Design Constraints for ADC  Constraints on ADC for neural recording not well defined in literature –Need to formulate constraints based on end result of the processing Spike-sorting process [3]

3. 3 Strategy for Defining Specifications  Sample neural data –Read from Neuralynx format into Matlab –Quantized and converted back into Neuralynx format  Osort software used for spike sorting [4] –Only known hardware-friendly clustering algorithm  Two clustering accuracy metrics are defined –Difference being inclusion of detection errors and false alarms [5] Sample Neural Data Spike-Sorting Non-ideal quantizer Spike-Sorting Compare classification results Bird’s eye view of analysis approach

4. 4 Number of bits needed  Most previous analysis calculates number of bits based on electrode thermal noise [6] –Making quantization noise equal to thermal noise degrades SNR by up to 3 dB –Thermal noise is uncorrelated with data while quantization noise is not  Knee of the curve lies around 9 bits –Reasonable assumption for the ADC –Matches commonly used number for ADC design in neural recording systems

5. 5 Clustering Accuracy vs. DNL  Non-monotonic behavior of curves precludes identification of clear trend –Need for statistical averaging

6. 6 CA Over Multiple DNL profiles  The mean classification accuracy is not a strong function of DNL –Indicates that the design of the ADC can sacrifice some DNL in favor of savings in power / area

7. 7 Variance of Accuracy  Higher DNLs also lead to higher variance in classification accuracy –Non-monotonic nature implies more averaging is needed

8. 8 Conclusions: Part 1  Summary of this work: –Created automated simulation setup for evaluation of impact of quantization error on spike-sorting results –Initial results point towards classification accuracy being a weak function of DNL –DNL around 1.5 LSB can be tolerated without significantly affecting classification accuracy –Higher DNLs lead to lower classification accuracy and higher variance in classification results  Future Work: –Simulation over larger number of DNL profiles and large number of data sets is required to establish validity of results –Similar analysis can be performed to include other non-idealities in analog front-end

9. 9 SAR ADC: Architecture  Operation governed by passive charge sharing  Size of capacitor array dictated by matching requirements and size of unit capacitor Architecture of SAR ADC [7]

10. 10 Ideal Case Model  Comparator makes decisions using voltage difference  Model ADC using charge conservation –Solve for differential and common mode voltages

11. 11 Symmetric Array Parasitics  Solution to the above system of simultaneous linear equations gives:

12. 12 Effect of Symmetric Parasitics  Common mode drift with each conversion step –Due to top and bottom plate capacitances charged to different values –Can affect comparator decisions  Gain error in ADC characteristics –Assuming parasitics are proportional to array capacitance

13. 13 Asymmetric Array Parasitics  Separate terms for V i f1 and V i f2, solve for V i f1 and V i f2

14. 14 Effect of Parasitic Mismatch  Dependence of O/P on absolute single-ended voltage leads to DNL –Differential Voltage now depends on absolute voltage values across parasitics –Estimated DNL of up to 3 LSB for 10% parasitics (with extreme mismatch in top and bottom plate cap)

15. 15 Modeling Junction Capacitances  In this analysis we focus on the non-linear S-D drain capacitances –Gate capacitances are expected not to significantly impact the linearity of the ADC

16. 16 Polynomial Approximation  Diode equation leads to non-integer exponents –Equations do not easily converge with numerical methods  Use polynomial fit instead –Fits equally well with monotonic characteristics over range of interest

17. 17 Modeling with Junction Parasitics  We have two equations in two variables and 5 th order  Re-write charge conservation with non-linear capacitors  Need to use numerical methods –Unique solution does not exist –The initial condition is derived by solving the equation without parasitic junction capacitances

18. 18 Effect of Junction Parasitics  Even with symmetric parasitic values the non-linearity of the junction caps leads to DNL in the ADC –Junction caps are charged to different voltages –ADC with 1.04  m switch for 60 fF capacitor has DNL contribution of 0.3 LSB due to parasitic junction capacitors –DNL contribution dependent on ratio between array capacitor and switch size

19. 19 Conclusions: Part 2  Summary of this work: –Modeled the effect of non-linearities on static characteristics of ADC –Matlab model integrated with existing model which also includes comparator mismatch and thermal noise –Parasitics of array capacitance lead to a CM drift –Mismatch in parasitic capacitances leads to DNL –Junction capacitances lead to DNL even when switches are perfectly symmetric  Future Work: –Validation of model with Cadence simulations –Modeling dynamic non-idealities of ADC –Combining Part 1 and Part 2 to have a application-specific optimized ADC –Check out for options to better performance of previous ADC using trends shown by models

20. 20 References/Acknowledgments REFERENCES [ 1] B. Murmann, “ADC Performance Survey 1997-2009”, [Online] Available: http://www.stanford.edu/~murmann/adcsurvey.html [2] B.Razavi, “Principles of Data Conversion System Design”, IEEE Press, 2005 [3] V. Karkare, S. Gibson, and D. Markovic, “A 130  W, 64-Channel Spike-Sorting DSP Chip”, ASSCC, Nov’09 [4] U. Reutishauser, E. Schuman, and A. Mamelak, “Online detection and sorting of extracellularly recorded action potentials in human medial temporal lobe recordings in vivo”, JNM, May’05 [5] S. Gibson, J.W.Judy, and D. Markovic, “Comparison of Spike-Sorting Algorithms for Future Hardware Implementation”, EMBC, Aug’08 [6] M.Chae, et. al., “Design Optimization for Integrated Neural Recording Systems”, JSSC, Sep’08 [7] J. Craininckx and G. Van der Plaas, “A 65fJ/Conversion-Step 0-to-50 MS/s 0-to- 0.7 mW 9b Charge Sharing SAR ADC in 90nm Digital CMOS”, ISSCC, Feb’07 ACKNOWLEDGMENTS Wolfgang Eberle, Vito Gianniani, Dejan Markovic, Sarah Gibson, and Ivan Gligorijevic.

21. 21 Questions / Comments?