1. Fundamentals of Digital Logic and Microcomputer Design

2. REFERENCE BOOK FUNDAMENTAL OF DIGITAL LOGIC AND MICROCOMPUTER DESIGN
FIFTH EDITION.
AUTHOR: M.RAFIQUZZAMAN
PUBLISHER: WILEY-INTERSCIENCE

3. Lecture 01: Introduction

4. Digital hardware • Logic circuits are used to build computer
hardware as well as other products (digital
hardware)
• Late 1960’s and early 1970’s saw a
revolution in digital capability
– Smaller transistors
– Larger chip size
• More transistors/chip gives greater functionality, but requires more complexity in the design process

5. Digital hardware • Integrated circuits are fabricated on silicon
wafers
• Wafers are cut &
packaged to form
individual chips
• Chips have from tens to
millions of transistors

6. How complex is a digital design?
• Complexity can, and generally does, surpass
human capability
– 16 million transistors/cm2 in 2004
– 100 million transistors/cm2 in 2014(?)
• Provides motivation for computer-based
design techniques
• Most engineering work is done with CAD
packages

7. Two design approaches – Relies on mathematical models
• Traditional
– Relies on mathematical
models
– Analytical approaches
– Provides insight and
understanding of problem
– Useful for small problems
– Inadequate for large
(real) problems
• CAD
– Software relies on
mathematical model and analytical approach
– Transparent to user
– Many details are abstracted
– Useful/required for real
problems

8. Types of chips Standard chips – Contain a small amount of circuitry
(<100 transistors)
– Performs simple functions
– 7400 series devices
• Programmable logic devices (PLD)
– Collection of gates with programmable
interconnections
– Function is configurable by designer/user
– Design with PLD is via a CAD tool

9. Types of chips(CONT.) Custom-designed chips
– Optimized for a specific task – better performance
– Larger amount of logic circuitry
– Cost of production is high
– Large volume required to justify cost

10. Digital Logic Introduction to Logic Circuits:
Variables, functions, truth tables,
gates and networks

11. Logic circuits Logic circuits perform operations on digital signals
– Implemented as
electronic circuits where
signal values are
restricted to a few
discrete values
• In binary logic circuits
there are only two
values, 0 and 1
• The general form of a
logic circuit is a
switching network

12. Boolean algebra Direct application to switching networks
– Work with 2-state devices → 2-valued Boolean
algebra (switching algebra)
– Use a Boolean variable (X, Y, etc.) to represent an
input or output of a switching network
– Variable may take on only two values (0, 1)
– X=0, X=1
– These symbols are not binary numbers, they
simply represent the 2 states of a Boolean
variable
– They are not voltage levels, although they
commonly refer to the low or high voltage
input/output of some circuit element

13. Variables and functions
The simplest binary element is a switch that
has two states
• If the switch is controlled by x, we say the
switch is open if x =0 and closed if x =1

14. Logic values as voltage levels
Vss is the minimum
voltage that can exist
in the system. We
will use Vss=0V.
VDD is the power
supply voltage. We
will use VDD =+5V.
VDD =+3.3V is also
common.
Exact levels of V0,max
and V1,min depend on
the implementation
technology

15. Transistor switches Logic circuits are built with transistors
We will assume a transistor operates as a simple
switch controlled by a logic signal x
The most popular type of transistor for implementing
a simple switch is the metal oxide semiconductor
field effect transistor (MOSFET)
Two types of MOSFETs
– N-channel (NMOS)
– P-channel (PMOS)
Early circuits relied on NMOS or PMOS transistors,
but not both
Current circuits use both NMOS and PMOS
transistors in a configuration called complementary
MOS (CMOS)

16. NMOS transistor as a switch

17. NMOS transistor as a switch
The transistor operates by
controlling the voltage VG at
the gate terminal
If VG is low, there is no
connection between the
source and the drain
terminals. The transistor is
turned off.
If VG is high, the transistor is
turned on and acts as a
closed switch between the
source and drain terminals.

18. PMOS transistor as a switch

19. PMOS transistor as a switch
The transistor operates by
controlling the voltage VG at
the gate terminal
• If VG is high, there is no
connection between the
source and the drain
terminals. The transistor is
turned off.
If VG is low, the transistor is
turned on and acts as a
closed switch between the
source and drain terminals.

20. NMOS and PMOS in logic circuits

21. NMOS and PMOS in logic circuits
When the NMOS transistor is turned on, its
drain is pulled down to Gnd
When the PMOS transistor is turned on, its
drain is pulled up to VDD
Because of the way transistors operate:
– An NMOS transistor cannot be used to pull its
drain terminal completely up to VDD
– A PMOS transistor cannot be used to pull its drain
terminal completely down to Gnd
Therefore, NMOS and PMOS transistors are
commonly used in pairs in CMOS circuits

22. CMOS logic gates A CMOS logic gate involves NMOS transistors
in a pull-down network (PDN) and PMOS
transistors in a pull-up network (PUN)
The functions realized by the PDN and PUN
networks are complements of one another
The PDN and PUN have equal numbers of
transistors, which are arranged so that the
two networks are duals of one another
– Wherever the PDN has NMOS transistors in series,
the PUN has PMOS transistors in parallel, and vice
versa

23. CMOS logic gates
For any given valuation of the input signals, either the PDN pulls Vf down to Gnd or the PUN pulls Vf up to VDD

24. CMOS NOT gate

25. CMOS NAND gate

26. CMOS NOR gate

27. CMOS AND gate

28. CMOS OR gate

29. CMOS non-inverting buffer

30. CMOS transmission gate

31. CMOS tri-state buffer

32. Variables and functions
Assume the switch
controls a light bulb as
shown
– The output is defined as
the state of the light L
• If the light is on → L=1
• If the light is off → L=0
• The state of L, as
function of x is
L(x)=x
• L(x) is a logic function
• x is an input variable

33. Variables and functions (AND)
Consider the possibility of two switches
controlling the state of the light
• Using a series connection, the light will be on
only if both switches are closed
– L(x1, x2)= x1· x2
– L=1 iff (if and only if) x1 AND x2 are 1

34. Variables and functions (OR)
Using a parallel connection, the light will be
on only if either or both switches are closed
– L(x1, x2)= x1+ x2
– L=1 if x1 OR x2 is 1 (or both)

35. Variables and functions
Various series-parallel connections would
realize various logic functions
– L(x1, x2, x3)= (x1 + x2) · x3

36. Variables and functions
What would the following logic function look like if implemented via switches?
– L(x1, x2, x3, x4)= (x1 · x2) + (x3 · x4 )

37. Inversion Before, actions occur when a switch is closed.
What about the possibility of an action
occurring when a switch is opened?
– L(x)=
– Where L=1 if x=0 and L=0 if x=1
• L(x) is the inverse (or complement) of x

38. Inversion of a function
If a function is defined as
– f(x1, x2)= x1+ x2
• Then the complement of f is
– (x1, x2)= = (x1+ x2)’
• Similarily, if
– f(x1, x2)= x1 · x2
• Then the complement of f is
– (x1, x2)= = (x1 · x2)’

39. Truth tables Tabular listing that fully describes a logic function
– Output value for all input combinations
(valuations)

40. Truth tables
Truth table for AND and OR functions of three variables

41. Truth tables of functions
If L(x,y,z)=x+yz, then the truth table for L
is:

42. Logic gates and networks
Each basic logic operation (AND, OR, NOT)
can be implemented resulting in a circuit
element called a logic gate
• A logic gate has one or more inputs and one
output that is a function of its inputs

43. Logic gates and networks

44. Logic gates and networks
A larger circuit is implemented by a network of gates
– Called a logic network or logic circuit

45. Logic gates and networks
Draw the truth table and the logic circuit for the following function
– F(a,b,c) = ac+bc’

46. Analysis of a logic network
To determine the functional behavior of a
logic network, we can apply all possible input signals to it

47. Analysis of a logic network
The function of a logic network can also be
described by a timing diagram (gives
dynamic behavior of the network)

48. Lecture 02 Number Systems & Codes

49. Positional representation
First consider integers
– Begin with positive only descriptions and expand to include
negative numbers
– Numbers that are positive only are unsigned and numbers
that can also assume negative values are signed
For the decimal system:
– A number consists of digits having ten possible values (0-9)
– Each digit represents a multiple of a power of 10
(123)10=1x102+2x101+3x100
In general, an integer is represented by n decimal digits
D=dn-1dn d1d0
Representing the value
V(D)=dn-1x10n-1 + dn-2x10n d1x101 + d0x100

50. Positional representation
Because the digits have 10 possible values and each
digit is weighted as a power of 10, we say that
decimal numbers are base-10 or radix-10 numbers
In digital systems we commonly use the binary, or
base-2, number system in which digits can be 0 or 1
– Each digit is called a bit
The positional representation is
B=bn-1bn b1b0
Representing a integer with the value
V(B)=bn-1x2n-1 + bn-2x2n b1x21 + b0x20

51. Positional representation The binary number 1101 represents the value V = 1x23 + 1x22 + 0x21 + 1x20 V = 8+4+1= 13 So (1101)2 = (13)10 • The range of numbers that can be represented by a binary number depends of the number of bits used In general, using n bits allows a representation of positive integers in the range 0 to 2n-1

52. Decimal/Binary conversion
A binary number can be converted to a decimal
number directly by evaluating the expression
V(B) = bn-1x2n-1 + bn-2x2n b1x21 + b0x20
using decimal arithmetic (by expansion)
Converting from a decimal to a binary number can
be preformed by successively dividing the decimal
number by 2 as follows:
– Divide the decimal number (D) by 2 producing a quotient
D/2 and a remainder. The remainder will be 0 or 1 (since we
divide by 2) and will represent a single bit (the LSB) of the
binary equivalent
– Repeatedly divide the generated quotient by 2 until the
quotient=0. For each divide, the remainder represents one
of the binary digits (bits) of the binary equivalent

53. Decimal/Binary conversion

54. Octal and hexadecimal numbers Positional notation can be used for any radix (base). If the radix is r, then the number K=kn-1kn k1k0 has the value
Numbers with radix-8 are called octal and
numbers with radix-16 are called hexadecimal (or hex)
– For octal, digit values range from 0 to 7
– For hex, digital values range from 0-9 and A-F

55. Numbers in different systems

56. Binary to hex or octal conversion
Group binary digits into groups of four (three) and assign each group a hexadecimal (octal) digit.
Binary-to-hex:
6 B 7
Binary-to-octal:
Hexadecimal-to-binary: A 1 9
Octal-to-binary:

57. Signed numbers • For signed numbers, in the binary system, the sign of the number is denoted by the left-most bit 0 = positive 1 = negative • For an n-bit number, the remaining n-1 bits represent the magnitude

58. Negative numbers For signed numbers, there are three common
formats for representing negative numbers
– Sign-magnitude
– 1’s complement
– 2’s complement
Sign-magnitude uses one bit for the sign (0 = +, 1= - )
and the remaining bits represent the magnitude of the number as in the case of unsigned numbers
For example, using 4-bit numbers
+5= =1101
+3= =1011
+7= =1111
Although this is easy to understand, it is not well suited for use in computers

59. 1’s complement representation
In the 1’s complement scheme, an n-bit negative number K, is obtained by subtracting its equivalent positive number, P, from 2n-1
K=(2n-1)-P
For example, if n=4, then
K=(24-1)-P=(15)10-P=(1111)2-P
-5=(15)10-5=(1111)2-(0101)2=(1010)2
-3=(15)10-3=(1111)2-(0011)2=(1100)2
From these examples, clearly the 1’s complement can be formed simply by complementing each bit of the number, including the sign bit
Numbers in the 1’s complement form have some drawbacks when used in arithmetic operations

60. 2’s complement representation
In the 2’s complement scheme, an n-bit negative number K, is obtained by subtracting its equivalent positive number, P, from 2n
K = 2n-P
For example, if n=4, then
K=24-P=(16)10-P=(10000)2-P
-5=(16)10-5=(10000)2-(0101)2=(1011)2
-3=(16)10-3=(10000)2-(0011)2=(1101)2
A simple way of finding the 2’s complement of a number is to add 1 to its 1’s complement

61. Rule for finding 2’s complements
Given a signed number, B=bn-1bn-2…b1b0, its 2’s complement, K=kn-1kn-2…k1k0, can be found by:
– examining all the bits of B from right to left and complementing all the bits after the first ‘1’ is encountered
For example if B=
Then the 2’s complement of B is K=
changed bits unchanged bits

62. Four-bit signed integers

63. Addition and subtraction
For sign-magnitude numbers, addition is simple, but if the numbers have different signs the task becomes more complicated
– Logic circuits that compare and subtract numbers are also needed
– It is possible to perform subtraction without this circuitry
– For this reason, sign-magnitude is not used in computers
For 1’s complement numbers, adding or subtracting some numbers may require a correction to obtain the actual binary result
For example, (-5)+(-2)=(-7), but when adding the binary equivalents of –5 and –2, the result is 0111 with and additional carry out of 1 which must be added back the the result to produce the final (correct) result of 1000

64. 2’s complement operations • For addition, the result is always correct • Any carry-out from the sign-bit position is simply ignored

65. 2’s complement subtraction The easiest way of performing subtraction is to negate the subtrahend and add it to the minuend Find the 2’s complement of the subtrahend and then perform addition

66. Other number representations
Previously, we dealt with binary integers
(signed or unsigned) in a positional number representation
Other number representations are also commonly used :
– Fixed-point: allows for fractional representation
– Floating-point: allows for high precision, very large and/or very small numbers
– Binary-coded decimal (BCD): another form for integer representation

67. Fixed-point numbers • A fixed-point number consists of integer and fraction parts • In positional notation, it is written as B=bn-1bn b1b0.b-1b-2…b-k • With a corresponding value of
The position of the radix point is assumed to be fixed

68. Fixed-point numbers For example, B=(01001010.10101)2
B=1x26+1x23+1x21+1x2-1+1x2-3+1x2-5 B=
B=( )10
B=(4A.A8)16
Logic circuits that deal with fixed-point numbers are essentially the same as those used for integers

69. Floating-point numbers
Fixed-point numbers have a range that is limited by the significant digits used to represent the number
For some applications, it is often necessary to deal with numbers that are very large (or very small)
For these cases, it is better to use a floating-point representation in which numbers are represented by a mantissa comprising the significant digits and an exponent of the radix R
The format is:
Mantissa x R Exponent
The numbers are usually normalized such that the radix point is placed to the right of the first non-zero digit
(for example, 5.234x1043 or 3.75x10-35)

70. IEEE single precision format The IEEE defines a 32-bit (single precision) format for floating point values – Sign bit (S): most significant bit – 8-bit exponent field (E): excess-127 exponent – 23-bit mantissa (M) • True exponent = E-127 • E=0 → 32-bit value=0 • E=255 → 32-bit value=∞

71. IEEE single precision format
The IEEE standard calls for a normalized mantissa, which means that the most significant bit is always set to 1.
It is not necessary to include this bit explicitly in the mantissa field
– If M is the value in the 23-bit mantissa field, the true (24-bit) mantissa is actually 1.M
The value of the floating point number is then
Value = (-1)S.M x 2E-127

72. Floating-point example
For example,
=+(1.11)2x2( )
=+(1.11)2x21
=+(11.1)2
=+(1x21+1x20+1x2-1)=(3.5)10
What is the following?

73. Binary-coded-decimal numbers
It is possible to represent decimal numbers simply by encoding each decimal digit in binary form
– Called binary-coded-decimal (BCD)
Because there are 10 digits to represent, it is necessary to use four bits per digit
– From 0=0000 to 9=1001
– ( )BCD=(78)10
BCD representation was used in some early computers and many handheld calculators
– Provides a format that is convenient when numerical
information is to be displayed on a simple digit-oriented display

74. ASCII character code
The most popular code for representing information in computers is used for both numbers and letters and some control codes
It is the American Standard Code for Information Interchange (ASCII) code
ASCII code uses seven-bit patterns to represent 128 different symbols including
– Digits (0-9)
– Lowercase (a-z) and uppercase (A-Z) characters
– Punctuation marks and other commonly used symbols
– Control codes
The 8-bit extended ASCII code is used to represent all of the above and another 128 graphics characters

75. Example ASCII character codes
• ( )ASCII=(41H)=‘A’ • ( )ASCII=(42H)=‘B’ • ( )ASCII=(61H)=‘a’ • ( )ASCII=(62H)=‘b’ • ( )ASCII=(30H)=‘0’ • ( )ASCII=(39H)=‘9’ • ASCII table given in the textbook

76. Introduction to Logic Circuits: Boolean algebra

77. Axioms of Boolean algebra
• Boolean algebra: based on a set of rules derived from a
small number of basic assumption(axioms)
• 1a 0·0=0
• 1b 1+1=1
• 2a 1·1=1
• 2b 0+0=0
• 3a 0·1=1·0=0
• 3b 1+0=0+1=1
• 4a If x=0 then x’=1
• 4b If x=1 then x’=0

78. Single-Variable theorems
From the axioms are derived some rules for dealing with single variables
• 5a x·0=0
• 5b x+1=1
• 6a x·1=x
• 6b x+0=x
• 7a x·x=x
• 7b x+x=x
• 8a x·x’=0
• 8b x+x’=1
• 9 x’’=x
• Single-variable theorems can be proven
by perfect induction
• Substitute the values x=0 and x=1 into the expressions and verify
using the basic axioms

79. Duality Axioms and single-variable theorems are expressed in pairs
– Reflects the importance of duality
• Given any logic expression, its dual is formed
by replacing all + with ·, and vice versa and
replacing all 0s with 1s and vice versa
– f(a,b)=a+b dual of f(a,b)=a·b
– f(x)=x+0 dual of f(x)=x·1
• The dual of any true statement is also true

80. Two & three variable properties
10a. x·y=y·x Commutative
• 10b. x+y=y+x
• 11a. x·(y·z)=(x·y)·z Associative
• 11b. x+(y+z)=(x+y)+z
• 12a. x·(y+z)=x·y+x·z Distributive
• 12b. x+y·z=(x+y)·(x+z)
• 13a. x+x·y=x Absorption
• 13b. x·(x+y)=x

81. Two & three variable properties
14a. x·y+x·y’=x Combining
• 14b. (x+y)·(x+y’)=x
• 15a. (x·y)’=x’+y’ DeMorgan’s
• 15b. (x+y)’=x’·y’ Theorem
• 16a. x+x’·y=x+y
• 16b. x·(x’+y)=x·y

82. Induction proof of x+x’·y=x+y

83. Perfect induction example

84. Proof (algebraic manipulation)
• Prove
– (X+A)(X’+A)(A+C)(A+D)X = AX
– (X+A)(X’+A)(A+C)(A+D)X
– (X+A)(X’+A)(A+CD)X (using 12b)
– (X+A)(X’+A)(A+CD)X
– (A)(A+CD)X (using 14b)
– (A)(A+CD)X
– AX (using 13b)

85. Algebraic manipulation
• Algebraic manipulation can be used to
simplify Boolean expressions
– Simpler expression => simpler logic circuit
• Not practical to deal with complex
expressions in this way
• However, the theorems & properties provide
the basis for automating the synthesis of
logic circuits in CAD tools
– To understand the CAD tools the designer should be aware of the fundamental concepts

86. Venn diagrams • Venn diagram: graphical illustration of
various operations and relations in an algebra
of sets
• A set s is a collection of elements that are
members of s (for us this would be a collection of Boolean variables and/or constants)
• Elements of the set are represented by the
area enclosed by a contour (usually a circle)

87. Venn diagrams

88. Venn diagrams

89. Venn diagrams (x+y)’= x’y’

90. Notation and terminology
• Because of the similarity with arithmetic
addition and multiplication operations, the
OR and AND operations are often called the
logical sum and product operations
• The expression
– ABC+A’BD+ACE’
– Is a sum of three product terms
– (A+B+C)(A’+B+D)(A+C+E’)
– Is a product of three sum terms

91. Precedence of operations
In the absence of parentheses, operations in a logical
expression are performed in the order
– NOT, AND, OR
• Thus in the expression AB+A’B’, the variables in the second
term are complemented before being ANDed together. That
term is then ORed with the ANDed combination of A and B (the AB term)

92. Precedence of operations
Draw the circuit diagrams for the following
– f(a,b,c)=(a’+b)c
– f(a,b,c)=a’b+c

93. Introduction to Logic Circuits: Synthesis using AND, OR, and NOT gates

94. Example logic circuit design
Assume we want to design a logic circuit with three inputs x, y, and z
• The circuit output should be 1 only when x=1 and either y or z (or both) is 1
– Three possible combinations
• x=1, y=0, z=1 => xy’z
• x=1, y=1, z=0 => xyz’
• x=1, y=1, z=1 => xyz
• The function could be written as
– f(x,y,z)=xy’z+xyz’+xyz (sum of products form)

95. Example logic circuit design

96. Example logic circuit design

97. Example logic circuit design
• Obviously, the cost (in terms of gates and connections) of this network is much less than the initial network
• The process of generating a circuit from a stated desired functional behavior is called synthesis
• Generation of AND-OR style networks from a
truth table is one of many types of synthesis
techniques that we will cover

98. Logic synthesis
• If a function f is described in a truth table, then an expression that generates f can by obtained (synthesized) by
– Considering all rows in the table where f= or
– By considering all rows in the table where f=0
• This will be an application of the principal of
duality

99. Minterms For a function of n variables f(a,b,c,…n)
– A minterm of f is a product of n literals (variables) in which each variable appears once in either true or complemented form, but not both
• f(a,b,c) -- minterm examples: abc, a’bc, abc’
• f(a,b,c) -- invalid examples: ab, c’, a’c
– An n variable function has 2n valid minterms

100. Minterms

101. Minterm notation

102. Minterm notation examples
• What is the minterm notation for the following function?
– f(a,b,c)=abc+a’bc+abc’+a’b’c
• What is the function (in terms of variables) if
the minterm notation is the following?
– f(a,b,c)= Σm(1,5,6,7)

103. Logic synthesis • Duality suggests that:
– If it is possible to synthesize a function f by
considering the truth table rows where f=1, then it should also be possible to synthesize f by considering the rows for which f=0.
• This approach uses the complement of
minterms, which are called maxterms

104. Maxterms

105. Maxterm notation

106. Maxterm notation examples
• What is the maxterm notation for the following function?
– f(a,b,c)=(a+b+c)(a’+b+c)(a+b+c’)(a’+b’+c)
• What is the function (in terms of variables) if
the maxterm notation is the following?
– f(a,b,c)= ΠM(1,5,6,7)

107. Sum-of-products and minimality

108. Form conversion

109. Design examples • Logic circuits provide a solution to a problem
• Some may be complex and difficult to design
• Regardless of the complexity, the same basic design issues must be addressed
1. Specify the desired behavior of the circuit
2. Synthesize and implement the circuit
3. Test and verify the circuit

110. Three-way light control
• Assume a room has three doors and a switch by each door controls a single light in the room.
– Let x, y, and z denote the state of the switches
– Assume the light is off if all switches are open
– Closing any switch turns the light on. Closing
another switch will have to turn the light off.
– Light is on if any one switch is closed and off if
two (or no) switches are closed.
– Light is on if all three switches are closed

111. Three-way light control

112. Multiplexer circuit
• In computer systems it is often necessary to choose data from exactly one of a number of sources
– Design a circuit that has an output (f) that is
exactly the same as one of two data inputs (x,y)
based on the value of a control input (s)
• If s=0 then f=x
• If s=1 then f=y
– The function f is really a function of three variables
(s,x,y)
– Describe the function in a three variable truth table

113. Multiplexer circuit

114. Multiplexer circuit

115. Car safety alarm • Design a car safety alarm considering four inputs
– Door closed (D)
– Key in (K)
– Seat pressure (S)
– Seat belt closed (B)
• The alarm (A) should sound if
– The key is in and the door is not closed, or
– The door is closed and the key is in and the driver is
in the seat and the seat belt is not closed

116. Car safety alarm

117. Adder circuit – C: carry bit
• Design a circuit that adds two input bits together (x,y) and produces two output bits (s and c)
– S: sum bit
• x=0, y=0 => s=0
• x=0, y=1 => s=1
• x=1, y=0 => s=1
• x=1, y=1 => s=0
– C: carry bit
• x=0, y=0 => c=0
• x=0, y=1 => c=0
• x=1, y=0 => c=0
• x=1, y=1 => c=1

118. Majority circuit
• Design a circuit with three inputs (x,y,z) whose output (f) is 1 only if a majority of the inputs are 1
– Construct a truth table
– Write a standard sum-of-products expression for f
– Draw a circuit diagram for the sum-of-products expression
– Minimize the function using algebraic manipulation
• During your minimization you can use any Boolean theorem, but leave the result in sum-of-products form
(generate a minimum sum-of-products expression)
– Draw the minimized circuit

119. Optimized Implementation of Logic Functions: Karnaugh Maps and Minimum Sum-of-Product Forms

120. 14a. x·y+x·y’=x 14b. (x+y)·(x+y’)=x
Karnaugh map
• The key to finding a minimum cost SOP or POS
form is applying the combining property
(14a for SOP or 14b for POS)
14a. x·y+x·y’=x 14b. (x+y)·(x+y’)=x
• The Karnaugh map (K-map) provides a
systematic (and graphical) way of performing
this operation
• Minterms can be combined by 14a when they
differ in only one variable
– f(x,y,z) = xyz+xyz’ = xy(z+z’) = xy(1) = xy
• The K-map illustrates this combination
graphically

121. Karnaugh map

122. Karnaugh map

123. Karnaugh map groupings

124. K-map groupings example

125. K-map groupings example

126. Three variable K-map

127. Example three-variable K-maps

128. Guidelines for combining terms
• Can combine only adjacent ‘1’s
• Can group only in powers of 2 (1,2,4,8, etc.)
• Try to form as large a grouping as possible
• Do not generate more groups than are
necessary to “cover” all the ‘1’s

129. Example groupings

130. K-map groupings example
• Draw the K-map and give the minimized logic
expression for the following.
– f(a,b,c)=Σm(1,2,3,4,5,6)
• Show the groupings made in the K-map

131. Four variable K-map

132. Four variable K-map

133. Example four-variable K-maps

134. Example groupings

135. Example groupings

136. Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions

137. Terminology
For a given term, each appearance of a variable (in true or
complemented form) is called a literal
– xyz’ => three literals
– abc’d => four literals
• Any ‘1’ or group of ‘1’s that can be combined on a K map
represents an implicant of a function
• An implicant is a prime implicant if it cannot be combined
with another implicant to remove a variable
• A collection of implicants that account of all valuations for
which a given function is ‘1’ is called a cover of that function
• Cost is the number of gates plus the total number of
inputs to all gates in the circuit

138. Terminology example

139. Prime implicants distinctions

140. Prime implicants example

141. Prime implicants example

142. Minimization of POS expressions
• POS minimization using K-maps proceeds
exactly as does SOP form except that groupings of ‘0’s in the K-map are used to form POS terms.
• K-map can be constructed directly from ΠM
expression for a function
• Place ‘0’s in the K-map for every maxterm in
the ΠM expression

143. Minimization of POS example

144. Minimization of POS example

145. K-map groupings example
Draw the K-map and give the minimized POS
logic expression for the following.
– f(a,b,c)=ΠM(0,2,3,5-7)
• Show the groupings made in the K-map

146. Incompletely specified functions
In digital systems it often happens that some
input conditions (i.e. some input values) can never happen
• An input combination that can never happen
is referred to as a don’t care condition
• As a circuit is designed, a don’t care condition can be ignored (i.e. the output for that condition can be treated as 0 or 1 in the truth table)
• A function that has don’t care condition(s) is
said to be incompletely specified

147. Example function with don’t cares

148. Example function with don’t cares

149. Minimum SOP form
1. Choose a minterm (a ‘1’ in the K-map) which is not yet
covered (don’t consider d’s).
2. Find all adjacent ‘1’s and ‘d’s (check the n adjacent cells for
an n-variable K-map).
3. If a single term (i.e. a single looping) covers the ‘1’ and all adjacent ‘1’s and ‘d’s then the looping forms an essential prime implicant. Loop the essential prime.
4. Repeat steps 1-3 until all essential prime implicants are located.
5. Find a minimum set of nonessential prime implicants to cover (loop) the remaining ‘1’s. If more than 1 set is possible, choose the set with the minimum number of literals (the largest grouping).

150. Minimum POS form
1. Choose a maxterm (a ‘0’ in the K-map) which is not yet covered (don’t consider d’s).
2. Find all adjacent ‘0’s and ‘d’s (check the n adjacent cells for an n-variable K-map).
3. If a single term (i.e. a single looping) covers the ‘0’ and all adjacent ‘0’s and ‘d’s then the looping forms an essential prime implicant. Loop the essential prime.
4. Repeat steps 1-3 until all essential prime implicants are located.
5. Find a minimum set of nonessential prime implicants to cover (loop) the remaining ‘0’s. If more than 1 set is possible, choose the set with the minimum number of literals (the largest grouping).

151. Optimized Implementation of Logic Functions: Multiple Output Circuits, NAND and NOR Logic Networks

152. Multiple output circuits
• In all previous examples we have considered
only single output functions
• In practice, these functions may be part of
some larger circuit that has many such functions
• Circuits that implement these functions may
be combined into a less costly single circuit
with multiple outputs by sharing some gates
needed in the implementation of the single
functions

153. Multiple output circuit example

154. Multiple output circuit example

155. Multiple output circuit example

156. Multiple output circuit example

157. NAND and NOR logic networks

158. DeMorgan’s theorem in gate terms

159. AND-OR and NAND-NAND networks

160. OR-AND and NOR-NOR networks

161. Exclusive OR (XOR) gate

162. Example XOR usage

163. XOR of three variables
• What is the canonical SOP form for the following expression? f(a,b,c) = a ⊕ b ⊕ c

164. Exclusive NOR (XNOR) gate

165. XNOR of three variables
• What is the canonical SOP form for the
following expression?
f(a,b,c) = a ≡ b ≡ c

166. Implementation Technology: Standard Chips and Programmable Logic Devices

167. Standard chips • A number of chips, each with a few logic gates, are
commonly used for small logic circuits
• These are known as 7400-series devices because
the part numbers always begin with the number 74
– Commonly packaged in a dual-inline package (DIP)
– Chips external connections are called pins or leads
– Two pins connect VDD and GND to supply power
for the chip.

168. A 7400-series chip

169. Implementation of f=ab+b’c

170. 7400-series chips • For each specific 7400-series chip, a number
of variants are fabricated with differing technologies
• For example:
– The 74LS00 is built with a technology called
transistor-transistor logic (TTL)
– The 74HC00 is fabricated using CMOS technology
• Most popular chips in use today are the CMOS variants

171. Programmable logic devices
• The function provided by each 7400-series device is fixed and each chip only provides a few logic gates
– These limitations make use of these chips
inefficient for building large circuits
• It is possible to fabricate chips with a large amount of circuitry (gates) but with a structure (interconnection) that is not fixed
– Called programmable logic devices (PLDs)

172. Programmable logic devices

173. Programmable Logic Array (PLA)

174. Gate-level diagram of a PLA

175. Customary schematic of a PLA

176. Programmable Array Logic (PAL)
• In a PLA both the AND and the OR planes are
programmable
• A simpler device with a fixed OR plane is called a programmable array logic (PAL) device
– As PALs are easier to manufacture and can operate faster than
a PLA, most practical applications using these small
programmable devices use the PAL structure

177. An example of a PAL

178. Extra circuitry in a PAL

179. Complex Programmable Logic Devices (CPLDs)
• For larger designs that single PLAs or PALs cannot accommodate, a
complex programmable logic device (CPLD) can be utilized
• A CPLD consists of multiple circuit blocks with internal wiring to
connect the blocks together and to the pins on the chip
• Each circuit block is similar to a PAL
– PAL-like blocks
• Commercial CPLDs have from 2 to more than 100 PAL-like blocks,
with 16 macrocells in each block
– Each macrocell is the equivalent of approximately 20 gates
– About 20,000 equivalent gates in a CPLD of 1000 macrocells
• Can construct moderately large logic circuits in a single chip

180. Structure of a CPLD

181. Field Programmable Gate Arrays
• To implement even larger circuits, it is convenient to use a different chip that has an even larger logic capacity
– A field programmable gate array (FPGA)
• Does not contain AND and OR planes
– Instead provides an array of logic blocks and
interconnection wires between the logic blocks
– Interconnection wires are arranged in horizontal and
vertical routing channels containing wires are
programmable switches
• Capable of implementing logic functions of millions of
equivalent gates

182. Structure of an FPGA

183. Optimized Implementation of Logic Functions: Multilevel Synthesis and Analysis

184. Multilevel NAND & NOR circuits
• Two-level circuits consisting of AND and OR gates
can easily be converted to networks that can be
realized only NAND and NOR gates
– A two-level AND-OR (SOP) circuit can be realized
(directly) as a two-level NAND-NAND circuit
– A two-level OR-AND (POS) circuit can be realized (directly) as a two-level NOR-NOR circuit
• The same approach can be used for
multilevel networks

185. AND-OR to NAND-NAND example

186. OR-AND to NOR-NOR example

187. Multilevel example

188. Multilevel example (NAND)

189. Multilevel example (NAND)

190. Multilevel example (NOR)

191. Multilevel example (NOR)

192. Multilevel conversion process
The basic topology (wiring) of a circuit does not change substantially when converting from AND and OR gates to either NAND or NOR gates
• It may be necessary to insert additional gates (to serve as NOT gates) that implement inversions not absorbed as a part of other gates in the circuit
• The resulting circuit may not be minimum (i.e. such as a minimum 2-level NAND-NAND or NOR-NOR network)

193. Multilevel conversion example

194. Analysis of multilevel circuits
In the previous examples, we synthesized multilevel circuits
• How can we easily determine a function that a given multilevel circuit implements?
– For two-level circuits we simply wrote out the SOP or POS form
equation from the circuit
– This is easy to visualize for two-level circuits
– This is more difficult for multilevel circuits because it is
difficult to write an expression for the circuit by inspection
• We can write an expression for a function by analyzing it at
intermediate points in the circuit
– Write expressions for each of these subfunctions
– Combine the subfunctions together into a single function

195. Multilevel circuit analysis

196. Multilevel circuit analysis

197. Arithmetic Circuits Unsigned Addition

198. Unsigned number addition

199. Unsigned number addition

200. Full adder circuit

201. Full adder circuit

202. Full adder circuit (decomposed)

203. Ripple-carry adder
In performing addition, we start from the least significant digit and add pairs of digits progressing to the most significant digit
• If a carry is produced in position i, it is added to
operands (digits) in position i+1
• A chain of full adders, connected in sequence, can perform this operation
• Such a configuration is called a ripple-carry adder because of the way the carry signal ‘ripple’ through from stage to stage

204. Ripple-carry adder

205. Ripple-carry adder
Each full adder introduces a certain delay before its si and ci+1 outputs are valid
– The propagation delay through the full adder
• Let this delay be Δt
• The carry out of the first stage c1 arrives at the second stage Δt after the application of the x0 and y0 inputs
• The carry out of the second stage c2 arrives at the third stage with a delay of 2Δt, and so on
• The signal cn-1 is valid after (n-1)Δt, and the complete sum is available after a delay of (n)Δt
• The delay obviously depends on the size of the numbers (i.e. the number of bits)

206. Arithmetic Circuits: Signed Numbers, Binary Adders and Subtractors

207. 2’s complement operations

208. 2’s complement subtraction

209. Adder and subtractor unit
The subtraction operation can be realized as the addition operation, using a 2’s complement of the subtrahend, regardless of the signs of the two operands
– It is possible to use the same adder circuit to perform
both addition and subtraction
• Recall that the 2’s complement can be formed from the 1’s complement simply by adding 1
• We can use the XOR operation to perform a 1’s complement
– Recall x⊕1=x’ and x⊕0=x
– If we are performing a subtract operation, 1’s complement
the subtrahend by XORing each bit with 1

210. Adder and subtractor unit

211. Arithmetic overflow
The result of addition or subtraction is supposed to fit within the significant bits used to represent the numbers
• If n bits are used to represent signed numbers, then the result must be in the range –2n-1 to +2n-1-1
• If the result does not fit in this range, we say that arithmetic overflow has occurred
• To insure correct operation of an arithmetic
circuit, it is important to be able to detect the
occurrence of overflow

212. Examples for determining arithmetic overflow

213. Arithmetic overflow

214. Fast Adder Designs, Tradeoffs, and Examples

215. Performance issues

216. Adder/subtractor performance

217. Adder/subtractor performance

218. Carry-lookahead adder

219. Carry-lookahead adder

220. Carry-lookahead (CLA) adder

221. Carry-lookahead (CLA) adder

222. Ripple-carry adder critical path

223. Carry-lookahead critical path

224. Carry-lookahead limitations

225. 32-bit adder design

226. Ripple-carry between blocks

227. Second level carry-lookahead circuit

228. Second level carry-lookahead circuit

229. Hierarchical CLA analysis

230. Combinatorial Circuit Building Blocks: Multiplexers

231. Multiplexers

232. Multiplexer implementations

233. 4-input multiplexer

234. Building a 4-input MUX

235. MUX application (a 2x2 crossbar)

236. Logic functions using MUXs

237. Logic functions using MUXs

238. Logic functions using MUXs

239. Logic functions using MUXs

240. Logic functions using MUXs

241. Logic functions using MUXs

242. Shannon’s expansion theorem

243. Shannon’s expansion theorem

244. Shannon’s expansion example

245. Shannon’s expansion example

246. Combinatorial Circuit Building Blocks: Decoders, Demultiplexers, Encoders and Code Converters

247. Decoders

248. 2-to-4 decoder circuit

249. 3-to-8 decoder

250. to-8 decoder

251. Demultiplexers

252. Encoders

253. Encoders

254. Priority encoders

255. Priority encoders

256. Code converters

257. BCD-to-7-segment decoder

258. BCD-to-7-segment decoder

259. BCD-to-7-segment decoder

260. Flip-Flops, Registers and Counters: Latches

261. Storage elements

262. Sequential circuits

263. Alarm control system

264. A simple memory element

265. Basic SR latch

266. Basic SR latch

267. Basic SR latch timing diagram

268. Basic SR latch timing diagram

269. Gated SR latch

270. Gated SR latch circuit

271. Gated SR latch timing diagram

272. Gated SR latch with NAND gates

273. Gated D latch

274. Gated D latch

275. Level versus edge sensitivity

276. Effects of propagation delays

277. Setup and hold times

278. Flip-Flops, Registers and Counters: Flip-Flops

279. Master-slave D flip-flop

280. Flip-flops

281. Master-slave D flip-flop

282. Master-slave D flip-flop

283. Edge-triggered flip-flop

284. Edge-triggered flip-flop

285. T flip-flop

286. Comparing D storage elements

287. T flip-flop

288. Clear and preset inputs

289. JK flip-flop

290. JK flip-flop

291. JK flip-flop timing diagram

292. Flip-Flops, Registers and Counters: Registers and Counters

293. Registers

294. Shift register

295. Shift right register

296. Parallel-access shift register

297. Parallel-access shift register

298. Counters

299. Up-counter with T flip-flops

300. Down counter with T flip-flops

301. Asynchronous counters

302. Synchronous counters

303. T flip-flop synchronous counter

304. Enable and clear capability

305. D flip-flop synchronous counter

306. Four-bit counter (D flip-flops)

307. Counters with parallel load

308. Parallel load counter

309. Synchronous Sequential Circuits: State Diagrams, State Tables

310. Synchronous sequential circuits

311. Moore versus Mealy machines

312. Basic design steps

313. Sequences of signals

314. State diagram

315. State diagram

316. State diagram

317. State diagram

318. Complete state diagram

319. State table

320. State assignment

321. State-assigned table

322. Next-state and output maps

323. State table and next-state maps

324. State table and output map

325. Circuit diagram

326. Timing diagram

327. Synchronous Sequential Circuits: Implementations using D-type, T-type and JK-type Flip-Flops

328. Counter design example

329. Counter state diagram

330. Counter state table

331. State-assigned state table

332. D-type flip-flop implementation

333. State table and next-state maps

334. Circuit diagram (D flip-flop)

335. Design using other flip-flop types

336. Transition tables

337. T-type flip-flop implementation

338. Excitation table and K-maps

339. Circuit diagram (T flip-flop)

340. JK-type flip-flop implementation

341. JK-type flip-flop implementation

342. Excitation table and K-maps

343. Excitation table and K-maps

344. Circuit diagram (JK flip-flop)