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Hybrid Activities for ABC130 1. 2 Aim to freeze thermo-mechanical layout next week in readiness for submission Will make use of a resistive serpentine.

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Presentation on theme: "Hybrid Activities for ABC130 1. 2 Aim to freeze thermo-mechanical layout next week in readiness for submission Will make use of a resistive serpentine."— Presentation transcript:

1 Hybrid Activities for ABC130 1

2 2 Aim to freeze thermo-mechanical layout next week in readiness for submission Will make use of a resistive serpentine trace embedded on inner layer as heating element/ASIC Component layer stays as is Retain bond pad detail and tracking for wire-bond evaluation SMD pads retained – allows tooling and wire-bond evaluation (component clashes etc.) Plan to meet with Roy (& interested parties) to discuss tape layout for thermo-mechanicals Ideally would like tape to have feature detail which is close to that of final object In this instance it will be a SP tape ABC130 Thermo-mechanicals Resistive trace on inner layer for a single asic Trace geometry is 300µm x 18µm x 75mm per asic location Trace resistance per asic is ~225mΩ Total resistance is ~2.5 Ω/hybrid (10 x ABC130 + HCC) Expected Hybrid Power ~2W (excludes sensor contribution of 1W) 5W total/module 2.5V/1A across thermo-mechanical hybrid results in 5W/module 65W/Stave side (65V/1A)

3 3 Planning for ABC130 Hybrids – without HCC ABC130 and HCC submissions being done sequentially Results in ABC130 arriving ~3(?) months before HCC Will plan for ABC130 evaluation but without HCC First at single chip level – followed by hybrid and then module Important to confirm that ABC130 works as expected when attached to a sensor For hybrid/module evaluation propose using an FPGA in place of HCC FPGA acts as a ‘blank canvas’ – program to suit required configuration First implementation will be as basic I/O buffer Connectivity will match closely that of single chip evaluation board Speeds up evaluation of ASIC(s) on hybrid as DAQ changes should be minimal Then move on to HCC implementation Necessitates changes to DAQ Candidate device identified – Xilinx Spartan 3AN series (XC3S50AN) Comes with integrated config memory, 2 x DCMs, 50 diff I/O, LVCMOS Offers a single chip solution as small as 15mm x 15mm (Fine-Pitch Thin BGA) Impacts upon hybrid layout – not realistic to add FPGA to hybrid Will hook up to FPGA which is mounted external to hybrid ABC130 – HCC connectivity will now be brought to edge of hybrid

4 4 Planning for ABC130 Hybrids – without HCC Hybrid Comes on pluggable PCB Data I/O To DAQ HCC First tests of HCC come on PCB carrier?


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