1. TX Application Architecture WINLAB – Rutgers University Date : July 27th 2009 Authors : Prasanthi Maddala, prasanthi.m@gmail.comprasanthi.m@gmail.com Khanh Le, kle@winlab.rutgers.edukle@winlab.rutgers.edu Ivan Seskar, seskar@winlab.rutgers.eduseskar@winlab.rutgers.edu

2. WGNG - Overview 2 Revision History IssueDateAuthor(s)Notes 1.110/27/09kleUpdated Application Block. Added RMAP interface.

3. WGNG - Overview 3 Tx Application Block

4. WGNG - Overview 4 OCRP provides a control block and a register map to support the application. The Application RMAP is optional. The user may opt out this option and only use the User Specific RMAP instead. The user may or may not use these blocks, i.e., the user application may contain its own control logic and its own register map (optional). The user application must conform to the interface provided by OCRP

5. WGNG - Overview 5 Application Control On receiving a new application request signal, the application control block informs the user application about the new data by making the data_avl signal high. As long as more data is available, it sends a 32 bit word to the user application whenever it gets a request.

6. WGNG - Overview 6 Application Control – System Control Interface Signal NameIn/OutWidthDescription App_reqIn1Application processing request signal. Active high. This indicates that data/control frames are available within Buffer. Application shall fetch data/control information using App_type, App_ptr and App_size information. App_typeIn2Type of frame within Buffer : 00 – control 01 – data Others – reserved App_ptrIn16Address pointer to location of data/control frames App_sizeIn16Size of data/control frames App_doneOut1Application processing done signal. Indicates that Application block has completed the processing request. System Control may assert a new request. Active High.

7. WGNG - Overview 7 Application Control – Buffer Interface Signal NameIn/OutWidthDescription Buf_rdOut1Buffer read signal. Active high, requesting for data stored at the address given out on buf_addr bus. Buf_addrOut16Buffer address from which data is to be read Buf_dataIn32A data word from the buffer

8. WGNG - Overview 8 Application Control – User Application Interface Signal NameIn/OutWidthDescription Data_reqIn1Data request signal. The user application requests for a new data word by making this signal high. Data_avlOut1Data available signal. Indicates that data is available for the user application. The user application should send a data request only when the data_avl signal is high. Data_enOut4Data enable signal indicating which bytes of the data word given to the user application are valid. Valid combinations are 0000 - data word not valid 0001 - LS byte valid 0011 - 2 LS bytes valid 0111 - 3 LS bytes valid 1111 - all bytes valid DataOut32Data word

9. WGNG - Overview 9 Application RMAP OCRP provides a programmable Register Map to support the application level control/status reporting purposes. Control register values are sent through control commands, which are parsed by the system control and written to the Register map. The register map also contains status registers, interrupt registers and RAMs. All these can be put to use once the receiver chain is designed. In the transmit path, only the control registers are being used. Above figure shows the ‘Other IO’ ports to indicate the presence of the interrupt registers etc.

10. WGNG - Overview 10 Application Register Map Interface (connects to System Control IF) Signal NameIn/OutWidthDescription csIn1Chip-select signal e.g. enable signal. This signal will be edge triggered inside the RMAP block itself. The driver may be level signal or single pulse. rnwIn1Read or Not Write signal : ‘1’ – read operation ‘0’ – write operation User RMAP will perform an edge trigger operation and use that signal to parse rnw signal. addrIn16Address bus, user may not use all 16-bit address bus signals. dataIn3232-bit Data bus, user may not use all 32-bit data bus signals. rd_ackOut1Read cycle acknowledgement, single clock pulse. wr_ackOut1Write cycle acknowledgement, single clock pulse.

11. WGNG - Overview 11 Register Map – User Application Interface Signal NameIn/OutWidthDescription Ctrl_reg_n[31:0]Out32Nth control register for the user application. The user can program the register map to have N control registers and interpret the register values as required. Stat_reg_n[31:0]In32Nth status register of the user application. The user can program the register map to have M status registers. Other IOOther IO to be explained later….

12. WGNG - Overview 12 User Application Above Figure shows the interface that the user application should conform to, while using the application data fetch block and the register map provided by OCRP. When the user application has its own data fetching logic and register map, it should have an interface same as the Application interface shown at the beginning of this document.

13. WGNG - Overview 13 User Application – Application Control/Report Interface (This is optional only, the user may create its own RMAP using the User RMAP interface) Signal NameIn/OutWidthDescription Ctrl_reg_n[31:0]In32Nth control register for the user application. The user can program the register map to have N control registers and interpret the register values as required. Stat_reg_n[31:0]Out32Nth status register of the user application. The user can program the register map to have M status registers. Other IOOther IO to be explained later…. User Application – RMAP Interface (This is optional only, the user may the control signals coming from Application layer e.g. Application Control/Report interface) Signal NameIn/OutWidthDescription csIn1Chip-select signal e.g. enable signal. This signal will be edge triggered inside the RMAP block itself. The driver may be level signal or single pulse. rnwIn1Read or Not Write signal : ‘1’ – read operation ‘0’ – write operation User RMAP will perform an edge trigger operation and use that signal to parse rnw signal. addrIn16Address bus, user may not use all 16-bit address bus signals. dataIn3232-bit Data bus, user may not use all 32-bit data bus signals. rd_ackOut1Read cycle acknowledgement, single clock pulse. wr_ackOut1Write cycle acknowledgement, single clock pulse.

14. WGNG - Overview 14 User Application - Application Control Interface (As defined in Application Control – user application interface) User Application - Buffer Interface Signal NameIn/OutWidthDescription Buf_dataIn32Data word that comes out of the buffer on sending a data_req. Data_en from the application data fetch block indicates which bytes of this word are valid. Signal NameIn/OutWidthDescription Data_reqOut1Data request signal. The user application requests for a new data word by making this signal high. Data_avlIn1Data available signal. Indicates that data is available for the user application. The user application should send a data request only when the data_avl signal is high. Data_enIn4Data enable signal indicating which bytes of the data word given to the user application are valid. Valid combinations are 0000 - data word not valid 0001 - LS byte valid 0011 - 2 LS bytes valid 0111 - 3 LS bytes valid 1111 - all bytes valid DataIn32Data word

15. WGNG - Overview 15 User Application – DAC Interface Signal NameIn/OutWidthDescription Data_out_validOut1DAC Data valid Tx_data_iOut16DAC I signal Tx_data_qOut16DAC Q signal

16. WGNG - Overview 16 User Application – Example 1 This example uses the application data fetch block and register map provided by OCRP. The application consists of a sine wave generator, an additive white gaussian noise generator and a modulator. One of these blocks can be selected by sending a control command to the system. Data can be sent to the modulator by a data command.

17. WGNG - Overview 17 User Application Example 1 – Register Map Interface For this user application, the register map is programmed to have 2 control registers, and no other registers. As shown below, only a few of the register bits are used by the user application. Signal NameIn/OutWidthDescription Ctrl.mod.scheme[1:0]Out2Modulation scheme. These bits represent the modulation scheme to be used 00 – PAM 01 - PSK 10 - QAM Ctrl.mod.sym_size[2:0]Out3These bits give the symbol size. Ctrl.mcr.app_type[3:0]Out4Application type – these bits are used as the mux select input to select an application 0000 – AWGN 0001 – Sine 0010 - Modulator

18. WGNG - Overview 18 Modulator Above Figure shows the modulator block used in Example 1 The modulator has 1. Control Block – this block interacts with the application data fetch block (looking at the data_avl signal and requesting for data when necessary) and passes on 4 bits of data per clock cycle to the data processing block. When the symbol size = n<4 bits, then it pads n bits of data with zeros. Ex: when the symbol size is 2 and the data bits are BB then the control block gives 00BB to the data processing block. 2. Data Processor – this block takes in 4 bits of data and maps it to a 16 bit I signal and a 16bit Q signal, based on the modulation scheme selected.

19. WGNG - Overview 19 Modulator Control - Application Control Interface (As defined in Application Control– user application interface) Signal NameIn/OutWidthDescription Data_reqOut1Data request signal. The user application requests for a new data word by making this signal high. Data_avlIn1Data available signal. Indicates that data is available for the user application. The user application should send a data request only when the data_avl signal is high. Data_enIn4Data enable signal indicating which bytes of the data word given to the user application are valid. Valid combinations are 0000 - data word not valid 0001 - LS byte valid 0011 - 2 LS bytes valid 0111 - 3 LS bytes valid 1111 - all bytes valid DataIn32Data word that comes out of the buffer on sending a data_req. Data_en from the application data fetch block indicates which bytes of this word are valid.

20. WGNG - Overview 20 Modulator Control – Modulator Data Proc. Interface Signal NameIn/OutWidthDescription Data_validOut1Data valid signal. Active high, indicating that the 4 bit data on ‘data’ bus is valid. Data[3:0]Out44 bits of data to the modulator. This data is padded according to the symbol size. When the symbol size is n<4, then n LSBs contain the actual data and 4-n MSBs are 0s, padded by the modulator control.