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12/10/01 - Cecilia Gerber UIC Slide 1 Testing Card specifications l Will be used in the Run2b SASEQ-based test stands  40+16+15 needed. Build 75, two.

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Presentation on theme: "12/10/01 - Cecilia Gerber UIC Slide 1 Testing Card specifications l Will be used in the Run2b SASEQ-based test stands  40+16+15 needed. Build 75, two."— Presentation transcript:

1 12/10/01 - Cecilia Gerber UIC Slide 1 Testing Card specifications l Will be used in the Run2b SASEQ-based test stands  40+16+15 needed. Build 75, two channels each. l Will replace the IB and the adapter card  Connects to SASEQ (50 conductor cable)  Takes two jumper cables (2 AVX connectors)  Will also have twisted pair cable connectors. l Should fit in the cool&dry box with the detectors  6U size or smaller l Functionally of the purple card is similar to the active adapter card, but with additional functions indicated in purple. C. Gerber (UIC) Silicon Electrical Meeting, 1/14/02 A. Nomerotski 1/15/02

2 12/10/01 - Cecilia Gerber UIC Slide 2 New Test Card

3 12/10/01 - Cecilia Gerber UIC Slide 3 Testing Card specifications l two channels per printed circuit board l size ~20 sq. in. or best effort l voltage regulation of SVX4 power (and possibly board power if needed) l SVX4 voltage (8-pin header) controlled by HDI enable/disable from SASEQ l Output for temperature monitoring (and voltage monitoring?), options for monitors:  VMIC Scanning ADC (requires VME)  NWU microprocessor connected to PC via serial link ?  voltmeter

4 12/10/01 - Cecilia Gerber UIC Slide 4 Specifications (cont.) l HV (silicon bias) supplied via a LEMO connector, and controlled by HDI enable/disable from the SASEQ l CAL-SR LEMO connector (two connectors) l fuses (resettable if feasible) on SVX4 power, and board power l Dvalid delay provision; SIP l clock conversion from TTL to low-voltage differential l one input 50-conductor connector from SASEQ

5 12/10/01 - Cecilia Gerber UIC Slide 5 Specifications (cont.) l Target date: July '02 for working prototype.  set on specs by 1/31/01  First iteration (2 stuffed boards) by May 02  10-15 working boards at Fermilab on 7/1/02 l Probable cost:  ~$25K, includes production of prototypes and ONE turnaround  + $5-7K if second turnaround is needed.  two channel interface card cost was $40-45K (for reference)


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