1. DATA-PROCESSING CIRCUITS Unit - 2

2. Multiplexers Multiplex means many into one. A Multiplexer is a circuit with many inputs but only one output. By applying control signals, we can steer any input to the output. Thus it is called a data selector and control inputs are termed as select inputs. Block diagram of multiplexer

3. Multiplexer types: 2-to-1 (1 select line) 4-to-1 (2 select lines) 8-to-1 (3 select lines) 16-to-1 (4 select lines) 4-to-1 Multiplexer truth table: Logic equation of the circuit: Y = A’B’.D 0 + A’B.D 1 + AB’.D 2 + A B.D 3 Ex: If A=0, B=0 Y=0’0’.D 0 +0’.0D 1 +0.0’D 2 +0.0D 3 Y=D 0 InputsOutput ABY 00D0D0 01D1D1 10D2D2 11D3D3

4. 4-to-1 Multiplexer logic circuit:

5. 8-to-1 Multiplexer ABCY 000D0 001D1 010D2 011D3 100D4 101D5 110D6 111D7 Logic circuit Truth Table Logic equation of the circuit: Y = A’B’C’.D 0 + A’B’C.D 1 + A’BC’.D 2 +…………..+ ABC’.D 6 +ABC.D 7

6. 16-to-1 Multiplexer Logic circuit Truth Table ABCDY 0000D0 0001D1 0010D2 0011D3 0100D4 0101D5 0110D6 0111D7 1000D8 1001D9 1010D10 1011D11 1100D12 1101D13 1110D14 1111D15

7. The input bits are labeled D0 to D15. Only one these is transmitted to the output. Which one depends on the value of ABCD, the control input. For instance, when ABCD=0000 Y=D 0 Logic equation of the circuit: Y = A’B’C’D’.D 0 + A’B’C’D.D 1 + A’B’CD’.D 2 +….. ……..+ ABCD’.D 14 +ABCD.D 15

8. The 74150 When 16-to-1 Multiplexer’s OR gate changed to NOR gate, the effect is, we get the complement of the selected data bit rather than the data bit itself. NOR gate, For instance, when ABCD=0111, the output is Y=D’ 7 This is the Boolean equation for a typical transistor-transistor logic (TTL) multiplexer because it has an inverter on the output that produces the complement of the selected data bit.

9. The 74150 is a 16-to-1 TTL multiplexer with the following pin diagram. The output Y = D n ’ where n is the decimal equivalent of ABCD.

11. Truth table of 74150

12. Multiplexer Logic Digital design usually begins with a truth table. Standard methods for implementing a truth table: SOP, POS and multiplexer solution. Ex: Use 74150 to implement a below given truth table. ABCDY 00001 00010 00101 00111 01001 01011 01100 01110 10001 10011 10101 10111 11001 11011 11100 11111

13. Bubbles on Signal lines Data sheets often show inversion on some of the signal lines. For instance, bubble on pin 10 – indicates that output is complement of the selected data bit. - bubble on the STROBE input (pin 9) – -Multiplexer is active (enabled) when the STROBE is low and inactive (disabled) when it is high. So the STROBE is called an active-low signal; it causes something to happen when it is low rather than when it is high.

14. Universal Logic Circuit Multiplexer sometimes is called universal logic circuit because 2 n -to-1 multiplexer can be used as a design solution for any n variable truth table. Realization of a 4 variable truth table by 16-to-1 multiplexer.  This Truth table can be realized using an 8-to-1 multiplexer.  Procedure adopted here is entered variable map.

15. Realize Y = F(A,B,C,D)=Σm(0, 2, 3, 4,5, 8, 9, 10, 11, 12, 13, 15) using 8-to-1 multiplexer.

16. Multiplexer Nibble Multiplexer:

17. Demultiplexers Demultiplex means one into many. A demultiplexer is a logic circuit with one input and many outputs. The 74154 (1-to-16 demultiplexer)

18. DeMultiplexer types: 1-to-2 (1 select line) 1-to-4 (2 select lines) – IC 74155 1-to-8 (3 select lines) – IC 74138 1-to-16(4 select lines) – IC 74154 Select lines determines which output the input line is connected to.

19. 1-to-4 Demultiplexer

20. 1-to-16 Demultiplexer

21. The 74154 Pinout diagram Logic diagram

22. 74154 Truth Table

23. Decoder A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to a maximum of 2 n unique output lines. 2:4 DECODER TRUTH TABLE: INPUTOUTPUT ABY0Y1Y2Y3 001000 010100 100010 110001

24. 2:4 DECODER Boolean Expression Y 0 = A’B’ Y1 = A’B Y 2 = AB’ Y 3 = AB

25. Decoders msb

26. Decoders are used in many types of applications. One example is in computers for I/O selection as in previous slide Computer must communicate with a variety of external devices called peripherals by sending and/or receiving data through what is known as input/output (I/O) ports Each I/O port has a number, called an address, which uniquely identifies it. When the computer wants to communicate with a particular device, it issues the appropriate address code for the I/O port to which that particular device is connected. The binary port address is decoded and appropriate decoder output is activated to enable the I/O port Binary data are transferred within the computer on a data bus, which is a set of parallel lines

27. 1-OF-16 Decoder A decoder is similar to a demultiplexer, with one exception—there is no data input. The only inputs are the control bits ABCD. This logic circuit is called 1-of-16 decoder because 1 of the 16 output line is high.

28. Using 74154 as Decoder

29. BCD-to-Decimal Decoder BCD is an abbreviation for binary-coded decimal. The BCD code expresses each digit in a decimal number by its nibble equivalent. To anyone using BCD code, 0100 0010 1001 is equivalent to 429. Pinout diagram of 7445

30. Example: Using a 3-to-8 decoder, design a logic circuit to realize the following Boolean function F(A,B,C) =  m(2, 3, 5, 6, 7) Example: Using two 2-to-4 decoders, design a logic circuit to realize the following Boolean function F(A,B,C) =  m(0, 1, 4, 6, 7)

31. Encoders An encoder has  2 N inputs  N outputs An encoder converts an active input signal into a coded output signal. An encoder outputs the binary value of the selected (or active) input. An encoder performs the inverse operation of a decoder.

32. An encoder is a combinational logic circuit that essentially performs a “reverse” of decoder functions. An encoder accepts an active level on one of its inputs, representing digit, such as a decimal or octal digits, and converts it to a coded output such as BCD or binary. Encoders can also be devised to encode various symbols and alphabetic characters. The process of converting from familiar symbols or numbers to a coded format is called encoding.

33. Decimal-To-BCD Encoder C

34. The 74147 Pinout diagramLogic diagram

36. Exclusive-OR Gates The exclusive-OR gate has a high output only when an odd number of inputs is high. Y=A B + A B A0011A0011 B0101B0101 Y0110Y0110 XOR gate Logic symbol Truth Table

37. Parity Generator and Checkers Even parity means an n-bit input has an even numbers of 1s. For instance, 110011. Odd parity means an n-bit input has an odd number of 1s. For instance, 110001. Parity Checker:  Ex-OR gate

38. Parity Generation Application To check data transmission errors Odd parity generation

39. The 74180 – TTL parity generator-checker

40. Using 74180 to generate odd parity

41. CLOCKS AND TIMING CIRCUITS

42. Clock waveforms Static digital logic levels: Voltage levels that do not change with time. Dynamic digital logic levels: Voltage levels that change with time. System Clock: It is the clock signal that advances the system logic through its sequences of steps. Typical clock wave form used in a digital system.

43. Ideal clock waveforms. Note: Clock need not to be the perfectly symmetrical waveform. It could be simply series of positive (or negative) pulses as shown in fig(b) The main requirement is that the clock be perfectly periodic, and stable.

44. Each signal in the below figure defines a basic timing interval during which logic operations must be performed. The basic timing interval is defined as the clock cycle time Clock cycle time – It is equal to one period of the clock wave form.  Thus all logic elements must complete their transitions in less than one clock cycle time.

45. Synchronous Operation Nearly all of the circuits in a digital system (computer) change states in synchronism with the system clock. A change of state will either occur as the clock transition from low to high or as it transition from high to low. The low to high transition is frequently called the positive transition (PT). A circuit that changes state at this time is said to be positive-edge-triggered The high to low is called the negative transition (NT). A circuit that changes state at this time is said to be negative-edge-triggered.

46. Virtually all circuits in a digital system are either positive-edge-triggered or negative-edge- triggered, and thus are synchronized with the system clock. There are few exceptions – The operation of push button (RESET) by a human operator might result in an instant change of state that is not in synchronism with the clock. This is called an asynchronous operation.

47. Characteristics The clock waveform shown above the timeline is a perfect, ideal clock.

48. Characteristics of ideal clock: 1. Clock levels must be absolutely stable.  Clock is high – level must hold steady value of +5V (between points a and b)  Clock is low – level must be unchanging of 0 V. (between points b and c)  In actual practice, the stability of the clock is much more important than the absolute value of the voltage level.  Ex: Steady, unchanging +4.8V is acceptable instead of +5.0 V.

49. 2. Time required for the clock levels to change from high to low or vice versa - An ideal clock has zero transition time. - Oscilloscope trace - Expanded Oscilloscope trace 3. Defines that an ideal clock is its frequency stability. The frequency of the clock should be steady and unchanging over a specified period of time. Short-term stability: Not to vary much Long-term stability: deals with longer periods of time.

50. Propagation Delay Time:  Propagation delay t p is the time between a PT (or a NT) at the input of a digital circuit and the resulting change at the output.  Propagation delay = t p ≈ t pLH ≈ t pHL

51. Pulse-Forming Circuits

52. Schmitt Trigger A Schmitt trigger is an electronic circuit that is used to detect whether a voltage has crossed over a given reference level. It has two stable states and is very useful as a signal-conditioning device. Given a sinusoidal waveform, a triangular wave any other periodic waveform, the schmitt trigger will produce a rectangular output that has sharp leading and trailing edges. Such fast rise and fall times are desirable for all digital circuits. Schmitt-trigger transfer characteristic.

53.  The value of V i that causes the output to jump from low to high is called a positive- going threshold voltage V T+  The value of V i causing the output to switch from high to low is called the negative-going threshold voltage V T-  The difference between the two threshold voltages is known as hysteresis Schmitt trigger inverter.

54. Functional Parts of 555 Timer IC: 555 Timer IC has basically three functional parts. They are as follows: Comparator: It is used to compare two voltages at the input level which is inverting (-) one and non inverting (+). If the voltage at the non-inverting is higher than other than the output is high. For ideal comparator input resistance is infinite. Voltage Divider: As the input resistance is infinite in the comparator so the voltage among all three resistors is being divided equally. Value across each resistor is Vin/3. Flip/Flop: Digital electronic device with memory. If the input is high while low at R then the output at Q is high. It means when S is high Q output is high and if R is high Q output is low.

55. Pin Description of 555 Timer: Trigger Input: If the input <1/3Vcc than at that condition output is high. It is useful in examining the timing capacitor discharging in a stable circuit. Threshold Input: This pin is attached to the first comparator at the non-inverting input terminal. If the threshold voltage is higher than (2/3) Vcc than the output is high at the comparator thus reset the output from high to low in the flip flop. Reset Input: As based on the internal condition of the flip-flop this pin reset the output of the flip-flop. To get rid of any noise interference an active low pin is attached to high state till any reset operator is required. So for most of the time it is attached to the supply voltage as in the figure. Control Input: An external voltage applied to this terminal changes the threshold as well as trigger voltage. Thus by imposing a voltage on this pin or by connecting a pot between this pin and ground, the pulse width of the output wave can be varied. when not used, the control pin should be bypassed to ground with a 0.01uF capacitor to prevent any noise problem.

56. Discharge Pin: When the timer output is low this pin is connected to 0 volts. It is used to discharge the timing capacitor in astable and monostable mode. Ground: The reference point or ground point of IC555 is connected to the ground terminal of the dc voltage source, Voltages of the entire circuit are measured with respect to this terminal. Output: The output of timer and the load is connected to this pin. Supply: This voltage must be a pure ripple free DC voltage which is obtained by connecting a positive regulated power supply.

58. 555 Timer - Astable Is a TTL-compatible integrated circuit (IC) that can be used as an oscillator to provide a clock waveform. It is basically a switching circuit that has two distinct output levels, neither of the output levels is stable. As a result the circuit switches back and forth between these two unstable states. In other words, the circuit oscillates and the output is a periodic, rectangular waveform.

59. Since neither output is stable, this circuit is said to be astable and is often referred to as a free- running multivibrator or astable multivibrator. The frequency of oscillation as well as the duty cycle are accurately controlled by two external resistors and a single timing capacitor. RESET DISCH THRES TRIG GND CONT OUT V CC C1C1 R1R1 R2R2 +V CC t1 t2  ---T--- 

60. Internal diagram of Astable 555 timer

61. Waveform for the Astable operation Voltage Across Timing Capacitor

62. In figure, the timing capacitor C is charged toward +Vcc through R A and R B. The charging time t 1 is given as t 1 = 0.693 (R A + R B ) C This is the time during which the output is high. The timing capacitor C is then discharged toward ground (GND) through the resistor R B. The discharge time t 2 is given as t 2 = 0.693 R B C This is the time during which the output is low.

63. The period T of the resulting clock waveform is the sum of t 1 and t 2. Thus, T = t 1 + t 2 = 0.693 ( R A + 2R B )C The frequency of oscillation is f = 1 / T = 1.44 / ( R A + 2R B )C The output of 555 times connected in this way outputs periodic rectangular wave but not the square wave. Because t1 and t2 are unequal. So duty cycle = t 2 / t 1 + t 2 = R B / R A + 2R B

64. 555 Timer - Monostable A switching circuit having one stable state and quasistable state. Since it has only one stable state, the circuit is termed as monostable mutivibrator or simply monostable. In stable state, the timing capacitor C is completely discharged by means of an internal transistor connected to C at pin 7. In this mode, the output voltage at pin 3 is at ground potential.

65. A negative pulse at the trigger input (pin 2) will cause the circuit to switch to its quasistable state. The output at pin 3 will go high and the discharge transistor at pin 7 will turn off, thus allowing the timing capacitor to begin charging toward Vcc. When the voltage across C reaches 2/3 Vcc, the circuit will regenerate back to its stable state. The discharge transistor will again turn on and discharge C to GND, the output will go back to GND, and the circuit will remain in this state until another pulse arrives at the trigger input.

66. The output of the monostable can be considered a positive pulse with a width t = 1.1 R A C Note: the input voltage at the trigger input must be held at +Vcc, and the negative pulse should then be applied when it is desired to trigger the circuit into its quasistable or timing mode.

67. IC 555 as monostable multivibrator

68. Monostable Nomograph By selecting suitable values of C and R in the ranges of 0.001uF to 100uF and 1kΩ to 10MΩ’s respectively, we can read the expected output frequency directly from the nomograph graph thereby eliminating any error in the calculations. In practice the value of the timing resistor for a monostable 555 timer should not be less than 1kΩ or greater than 20MΩ

69. Operational Amplifiers Amplifier which could be configured to perform variety of operations such as amplification, addition, subtraction, differentiation, and integration. Hence the name operational amplifiers. Is basically a voltage amplifier with extremely high voltage gain Ex: 741 OP-AMP has a typical gain 2 x 10 5 or 106 dB.

70. Op-Amp Symbol The two input terminals are denoted as the inverting and noninverting terminals respectively. The inverting terminal is universally indicated by a (-) symbol, and the noninverting terminal is indicated by a (+) symbol.

71. Op-amp Parameter and Idealised Characteristic Voltage gain = A = v o / v i in decibels (dB) 20 log (A) Input impedance = R in = v i / i i Differential input voltage = The difference between the voltages at the non-inverting input and the inverting input v d = v+ - v-

72. Open Loop Gain, (Avo) Infinite – The main function of an operational amplifier is to amplify the input signal and the more open loop gain it has the better. Open-loop gain is the gain of the op-amp without positive or negative feedback and for such an amplifier the gain will be infinite but typical real values range from about 20,000 to 200,000. Input impedance, (Zin) Infinite – Input impedance is the ratio of input voltage to input current and is assumed to be infinite to prevent any current flowing from the source supply into the amplifiers input circuitry ( Iin = 0 ). Real op-amps have input leakage currents from a few pico-amps to a few milli- amps.

73. Output impedance, (Zout) Zero – The output impedance of the ideal operational amplifier is assumed to be zero acting as a perfect internal voltage source with no internal resistance so that it can supply as much current as necessary to the load. This internal resistance is effectively in series with the load thereby reducing the output voltage available to the load. Real op-amps have output impedances in the 100- 20kΩ range. Bandwidth, (BW) Infinite – An ideal operational amplifier has an infinite frequency response and can amplify any frequency signal from DC to the highest AC frequencies so it is therefore assumed to have an infinite bandwidth. With real op-amps, the bandwidth is limited by the Gain- Bandwidth product (GB), which is equal to the frequency where the amplifiers gain becomes unity.

74. Inverting Amplifier In an inverting amplifier, the output voltage changes in an opposite direction to the input voltage. Assuming stable linear operation, the differential input voltage v d is forced to be zero, or v - = v +. + vf - i V - =0 i

75. Since v+ = 0 because the noninverting terminal is grounded, the inverting terminal is also forced to be at ground potential; that is v- = 0. This condition is referred to as a virtual ground, meaning that the inverting terminal is not really connected to ground, but it acts as if it were grounded from a voltage point of view. Since v- =0, the input voltage v i appears across R i. The input current i i is then i i = v i / R i

76. The current i i flows to the junction point at the amplifier inverting input terminal. However no current can flow into or out of the amplifier, the current must flow through R f. A voltage v f is then produced across R f, given by V f = R f i i = R f. v i / R i = R f / R i. v i Since the inverting input of the op-amp is at a virtual ground, the output voltage is the voltage across R f, but with the reference positive terminal on the left-hand side of R f. This leads to v o = - v f = - R f / R i.v i

77. Let A CL represent the closed-loop voltage gain of the circuit. We have A CL = v o / v i = - R f / R i Thus, the closed loop voltage gain is a simple resistance ratio and is independent of the open loop gain.

78. Non-inverting amplifier In a non-inverting amplifier, the output voltage changes in the same direction as the input voltage. Input signal is applied directly to the noninverting input. Assuming stable linear operation, the differential input voltage is forced to be zero, and thus v- = v+ = v i

79. This voltage appears across the resistance R i, so the current i i is readily determined as i i = v i / R i Since no current flows into or out of the op-amp inverting terminal, the current must be flowing through the resistance R f from the op-amp output. A voltage v f appears across R f and is V f = R f i i = R f v i / R i The voltage v i with respect to ground, the voltage v f, and the output voltage v o constitute a closed loop, and a Kirchhoff voltage law equation could be written if desired.

80. It can be readily deduced that v o = v i + v f = v i + R f. v i = 1 + R f v i R i R i The closed-loop voltage gain A CL is then given by A CL = v o = 1 + R f = R i + R f v i R i R i

81. SLE

82. MAGNITUDE COMPARATOR Magnitude comparator compares magnitude two n-bit binary numbers, say X and Y and activates one of these three outputs X=Y, X>Y and X<Y. a) Block diagram of Magnitude comparator (b) Truth table and (c) circuit for 1- bit comparator

83. MAGNITUDE COMPARATOR a) Functional diagram of IC 7485 and (b) 8-bit comparator from two 4-bit comparators.

84. Programmable Array Logic PAL is a programmable array of logic gates on a single chip.

85. Programmable Array Logic Programming A PAL  A PAL is different from a PROM because it has a programmable AND array and a fixed OR array. Y3=ABCD+ABCD+ABCD+ABCD Y2=ABCD+ABCD+ABCD Y1=ABC+ABC+ABC+ABC Y0=ABCD

86. Programmable Array Logic Commercially available PALs  10H8: 10 input and 8 output AND-OR  16H2: 6 input and 2 output AND-OR  14L4: 14 input and 4 output AND-OR- INVERT For these chip numbers, H stands for active- high output and L for active-low output.

87. Programmable logic Arrays PLAs, along with ROMs and PALs, are included in more general classification of ICs called programmable logic devices(PLDs). PLA PAL

88. HDL implementation of data processing circuits Hardware design of multiplexers using Verilog code. The behavioral model can be used to describe the 2 to 1 multiplexers in following different ways module mux2to1(A,D0,D1,Y); input A,D0,D1; // Circuit shown in Fig. 4-3(a) output Y; assign Y=(~A&D0)|(A&D1); endmodule module mux2to1(A,D0,D1,Y); input A,D0,D1; // Circuit shown in Fig. 4-3(a) output Y; assign Y= A ? D1 : D0; //Conditional assignment endmodule module mux2to1(A,D0,D1,Y); input A,D0,D1; // Circuit shown in Fig. 4-3(a) output Y; reg Y; always @ (A or D0 or D1) if (A==1) Y=D1; else Y=D0; endmodule module mux2to1(A,D0,D1,Y); input A,D0,D1; // Circuit shown in Fig. 4-3(a) output Y; reg Y; always @ (A or D0 or D1) case (A) 0 : Y=D0; 1 : Y=D1; endcase endmodule

89. Bus representation in HDL The Verilog code for demultiplexer/decoder. module demux1to4(S,D,Y); input [1:0] S; input D; output [3:0] Y; reg [3:0] Y; always @ (S or D) case ({D,S}) //Concatenation of D and S to give 3 bits, D is MSB 3’b100 : Y= 4’b0001; //Binary representation, refer to Section 2-5. If D=1, S=00, Y=0001 3’b101 : Y= 4’b0010; // if D=1, S=01, Y=0010 3’b110 : Y= 4’b0100; // if D=1, S=10, Y=0100 3’b111 : Y= 4’b1000; // if D=1, S=11, Y=1000 default : Y= 4’b0000; //For other combinations D=0, then Y=0000 endcase endmodule