1. Chapter Four Combinational Logic 1

2. C OMBINATIONAL C IRCUITS It consists of input variables, logic gates and output variables. Output is function of input only i.e. no feedback When input changes, output changes (after a delay) n inputsm outputs Combinational Circuits  2

3. C OMBINATIONAL C IRCUITS Analysis Given a circuit, find out its function Function may be expressed as: Boolean function Truth table Design Given a desired function, determine its circuit Function may be expressed as: Boolean function Truth table ? ? ? 3

4. A NALYSIS P ROCEDURE Boolean Expression Approach F 1 =T 2 +T 3= AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC T 2 =ABC T 1 =A+B+C F 2 =AB+AC+BC F’ 2 =( A’+B’ )( A’+C’ )( B’+C’ ) T 3 =AB'C'+A'BC'+A'B'C 4

5. A NALYSIS P ROCEDURE We can obtain the truth table directly from the logic diagram Truth Table Approach A B C F1F1 F2F2 0 0 0 = 0 T2 = 0 T1 = 0 0 F2 = 0 F’2 = 1 T3 = 0 0 0 5

6. 6 Full Adder Circuit

7. A NALYSIS P ROCEDURE Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 0100001000 0 1 1 1 A B C F1F1 F2F2 0 0 000 0 0 1 1 0 7

8. A NALYSIS P ROCEDURE Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 0100001000 0 1 1 1 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 0 1 0 8

9. A NALYSIS P ROCEDURE Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 0100101001 1 0 0 0 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 010 0 1 1 0 1 9

10. A NALYSIS P ROCEDURE Truth Table Approach = 1 1111111111 1 0 0 1 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 010 0 1 101 1 0 010 1 0 101 1 1 001 1 1 1 1 B 0101 A1010 C B 0010 A0111 C F 1 =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC 10

11. D ESIGN P ROCEDURE Given a problem statement: Determine the number of inputs and outputs Derive the truth table Simplify the Boolean expression for each output Produce the required circuit Example: Design a circuit to convert a “BCD” code to “Excess -3” code  4-bits  0-9 values  4-bits  Value+3 ? 11

12. D ESIGN P ROCEDURE BCD-to-Excess 3 Converter A B C D w x y z 0 0 0 0 1 1 0 0 0 10 1 0 0 0 0 1 00 1 0 0 1 10 1 1 0 0 1 0 00 1 1 1 0 1 1 0 0 0 0 1 1 01 0 0 1 0 1 1 11 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 x x C 111 B A xxxx 11 xx D C 111 1 B A xxxx 1 xx D C 11 11 B A xxxx 1 xx D C 11 11 B A xxxx 1 xx D w = A+BC+BDx = B’C+B’D+BC’D’ y = C’D’+CDz = D’ 12

13. 13

14. D ESIGN P ROCEDURE BCD-to-Excess 3 Converter w = A + B(C+D) x = B’(C+D) + B(C+D)’ y = (C+D)’ + CD z = D’ A B C D w x y z 0 0 0 0 1 1 0 0 0 10 1 0 0 0 0 1 00 1 0 0 1 10 1 1 0 0 1 0 00 1 1 1 0 1 1 0 0 0 0 1 1 01 0 0 1 0 1 1 11 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 x x 14

15. S EVEN -S EGMENT D ECODER (digital clock) a b c g e d f ? wxyzwxyz abcdefgabcdefg w x y za b c d e f g 0 0 1 1 1 1 1 1 0 0 0 0 10 1 1 0 0 0 0 0 0 1 01 1 0 1 1 0 1 0 0 1 11 1 1 1 0 0 1 0 1 0 00 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 01 0 1 1 1 1 1 0 1 1 11 1 1 0 0 0 0 1 0 0 01 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 11 1 1 1 0 1 1 1 0 x x x x x x x 1 0 1 1x x x x x x x 1 1 0 0x x x x x x x 1 1 0 1x x x x x x x 1 1 1 0x x x x x x x 1 1 x x x x x x x y 111 111 x w xxxx 11 xx z BCD code a = w + y + xz + x’z’b =... c =... d =... 15

16. B INARY A DDER Half Adder Adds 1-bit plus 1-bit Produces Sum and Carry HA xyxy SCSC x y C S 0 0 1 1 00 1 1 1 0 x + y ─── C S xyxy SCSC 16

17. B INARY A DDER Full Adder Adds 1-bit plus 1-bit plus 1-bit Produces Sum and Carry x y z C S 0 0 00 0 0 10 1 0 1 00 1 0 1 11 0 1 0 00 1 1 0 11 0 1 1 01 0 1 1 11 x + y + z ─── C S FA xyzxyz SCSC y 0101 x1010 z y 0010 x0111 z S = xy'z'+x'yz'+x'y'z+xyz = x  y  z C = xy + xz + yz 17

18. B INARY A DDER Full Adder xyzxyz SCSC xyzxyz SCSC S = xy'z'+x'yz'+x'y'z+xyz = x  y  z C = xy + xz + yz 18 Implementation of full adder in sum of products form

19. B INARY A DDER Implementation of Full Adder with two half adder and an OR gate. xyzxyz SCSC HA xyzxyz SCSC 19

20. B INARY A DDER c 3 c 2 c 1. + x 3 x 2 x 1 x 0 + y 3 y 2 y 1 y 0 ──────── Cy S 3 S 2 S 1 S 0 FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Binary Adder x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 S3S2S1S0S3S2S1S0 C0C0 C4C4 Carry Propagate Addition 20

21. Subscript i3210 Input carry0110 Ci 1011 xi 0011 yi Sum1110 Si Output carry0011 Ci+1 21

22. Carry propagation When the correct outputs are available The critical path counts : ( A 0, B 0, C 0 ) → C 1 → C 2 → C 3 → ( C 4, S 3 ) When 4-bits full-adder → 8 gate levels ( n -bits: 2 n gate levels) Figure 4.10 Full Adder with P and G Shown 22

23. B INARY A DDERS (P ARALLEL ) Reduce the carry propagation delay Employ faster gates Look-ahead carry (more complex mechanism, yet faster) Carry propagate: P i = A i  B i Carry generate: G i = A i B i Sum: S i = P i  C i Carry: C i+1 = G i + P i C i C 0 = Input carry C 1 = G 0 +P 0 C 0 C 2 = G 1 +P 1 C 1 = G 1 +P 1 ( G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0 C 3 = G 2 +P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 + P 2 P 1 P 0 C 0 23

24. C ARRY L OOK - AHEAD A DDER (1/2) Logic diagram Fig. 4.11 Logic Diagram of Carry Look-ahead Generator 24

25. C ARRY L OOK - AHEAD A DDER (2/2) 4-bit carry-look ahead adder Propagation delay of C 3, C 2 and C 1 are equal. Fig. 4.12 4-Bit Adder with Carry Look-ahead 25

26. B INARY S UBTRACTOR Use 2’s complement with binary adder x – y = x + (- y ) = x + y’ + 1 26

27. B INARY A DDER /S UBTRACTOR M : Control Signal (Mode) M = 0  F = x + y M = 1  F = x – y  F = x + y ’ + 1 y  0 = y y  1 = y' 27

28. O VER F LOW : When two numbers with n digits each are added and the sum is a number occupying n + 1 digits, we say that an overflow occurred. Unsigned Binary Numbers 2’s Complement Numbers FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Carry FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Overflow

29. 0 1 +70 0 1000110 +80 0 1010000 +150 1 0010110 1 0 -70 1 0111010 - 80 1 0110000 -150 0 1101010 29  An overflow cannot occur after an addition if one number is positive and the other is negative. since adding a positive number to a negative number produces a result whose magnitude is smaller than the larger of the two original numbers.  An overflow may occur when the two numbers added are both (+) or both (-). Consider 8 bit register (127 --- -128).

30. 30 T HE P ROBLEMS : 4.1, 4.3, 4.4, 4.6( A ), 4.10, 4.11, 4.13, 4.15

31. 31 BCD A DDER 4-bits plus 4-bits Operands : 0 to 9 This is called BCD adder. In order to add two decimal digits with a possible carry-in of 1, then the maximum sum is 19. The following table shows the sum when performed in binary and compared to the sum when performed in BCD. In both cases five outputs are needed. + x 3 x 2 x 1 x 0 + y 3 y 2 y 1 y 0 ──────── Cy S 3 S 2 S 1 S 0

32. 32

33. From the table, when the sum is greater than 9, a correction is needed. The correction is adding 6 to the binary sum. The BCD adder will then consist of the 4-bit binary adder. A second 4-bit binary adder is needed to add 6 to the sum when it is greater than 9. 01010 + 0110 = 10000 The required logic circuit needed to detect if correction is needed can be obtained as follows: C = K + Z 8 Z 4 +Z 8 Z 2 33

34. 34 BCD A DDER

35. B INARY M ULTIPLIER To multiply two 2-bit binary numbers B1 B0 and A1 A0, we may use half adders & AND gates. 35

36. 36

37. 37 For J multiplier bits and K multiplicand bits, we need ( J x K ) AND gates and ( J – 1) K -bit adders to produce a product of J + K bits. In the previous example, K = 4, J = 3, so we need 12 AND gates and 2 four-bit adders to produce a product of seven bits.

38. M AGNITUDE C OMPARATOR Compare 4-bit number to 4-bit number 3 Outputs: Expandable to more number of bits 0010, 1000 (Using XNOR Gates for equality) Magnitude Comparator A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 A B

39. M AGNITUDE C OMPARATOR

40. D ECODERS Extract “ Information ” from the code n -to- m line decoder ( n inputs, m <= 2 n output) Binary Decoder Example: 2-bit Binary Number Binary Decoder x1x0 x1x0 Only one lamp will turn on 0000 10001000

41. D ECODERS 2-to-4 Line Decoder I 1 I 0 Y 0 Y 1 Y 2 Y 3 0 1 0 0 0 0 10 1 0 0 1 00 0 1 0 1 0 0 0 1 BinaryDecoder I1I0 I1I0 Y0Y1 Y2Y3 Y0Y1 Y2Y3

42. D ECODERS 3-to-8 Line Decoder (Binary to Octal conversion) BinaryDecoder I2I1I0 I2I1I0 Y0Y1 Y2Y3Y4Y5 Y6Y7 Y0Y1 Y2Y3Y4Y5 Y6Y7

43. 43

44. D ECODERS “ Enable ” Control BinaryDecoder I1I0E I1I0E Y0Y1 Y2Y3 Y0Y1 Y2Y3 EI 1 I 0 Y 0 Y 1 Y 2 Y 3 0x 0 0 10 1 0 0 0 10 10 1 0 0 11 00 0 1 0 11 0 0 0 1

45. 45 4 x16 decoder constructed with two 3 x 8 decoders

46. D ECODERS Expansion E I 1 I 0 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 0 0 00 0 0 0 0 0 0 1 0 0 10 0 0 0 0 0 1 0 0 1 00 0 0 0 0 1 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 1 0 0 0 0 1 0 10 0 1 0 0 0 0 0 1 1 00 1 0 0 0 0 0 0 1 1 11 0 0 0 0 0 0 0 I 2 I 1 I 0 BinaryDecoder I0I1E I0I1E Y3Y2 Y1Y0 Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 I0I1E I0I1E Y3Y2 Y1Y0 Y3Y2 Y1Y0 3 x8 decoder constructed with two 2 x 4 decoders

47. D ECODERS Active-High / Active-Low I 1 I 0 Y 0 Y 1 Y 2 Y 3 0 1 0 0 0 0 10 1 0 0 1 00 0 1 0 1 0 0 0 1 I 1 I 0 Y 0 Y 1 Y 2 Y 3 0 0 1 1 1 0 11 0 1 1 1 01 1 0 1 1 1 1 1 0 BinaryDecoder I1I0 I1I0 Y0Y1 Y2Y3 Y0Y1 Y2Y3 I1I0 I1I0 Y0Y1 Y2Y3 Y0Y1 Y2Y3

48. I MPLEMENTATION U SING D ECODERS Each output is a minterm All minterms are produced Sum the required minterms Example: Full Adder S ( x, y, z ) = ∑(1, 2, 4, 7) C ( x, y, z ) = ∑(3, 5, 6, 7) x y z C S 0 0 00 0 0 10 1 0 1 00 1 0 1 11 0 1 0 00 1 1 0 11 0 1 1 01 0 1 1 11

49. A function with a long list of minterms requires an OR gate with a large number of inputs. If the number of minterms in the function is greater than 2 n /2, then F’ can be expressed with fewer minterms. So we use a NOR gate to sum the minterms of F’. The output of NOR gate complements this sum and generates the normal output F. 49

50. I MPLEMENTATION U SING D ECODERS WITH NAND GATES I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Decoder xyz xyz S C

51. E NCODERS Put “ Information ” into code (it generates the binary code corresponding to the input value). Binary Encoder Example: 4-to-2 Binary Encoder x 0 x 1 x 2 x 3 y 1 y 0 1 0 0 00 0 1 0 00 1 0 0 1 01 0 0 0 0 11 Binary Encoder y1y0 y1y0 x 0 x 1 x 2 x3 Only one switch should be activated at a time

52. E NCODERS Octal-to-Binary Encoder (8-to-3) I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 Y 2 Y 1 Y 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 1 00 0 1 0 0 0 0 0 1 0 00 1 0 0 0 0 0 1 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 1 0 0 0 0 01 0 1 0 1 0 0 0 0 0 01 1 0 1 0 0 0 0 0 0 01 1 1 BinaryEncoder Y2Y1Y0Y2Y1Y0 I7I6 I5I4I3I2 I1I0 I7I6 I5I4I3I2 I1I0

53. P RIORITY E NCODERS 4-Input Priority Encoder ( V is a valid bit indicator) PriorityEncoder VyxVyx D3D2 D1D0D3D2 D1D0

54. 54 1

55. 55

56. E NCODER / D ECODER P AIRS Y2Y1Y0Y2Y1Y0 I7I6 I5I4I3I2 I1I0 I7I6 I5I4I3I2 I1I0 I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Encoder Binary Decoder

57. M ULTIPLEXERS (D ATA S ELECTOR ) I T S ELECTS BINARY INFORMATION FROM ONE OF MANY INPUT LINES AND DIRECTS IT TO A SINGLE OUTPUT LINE. MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 Y 0 I0I0 0 1I1I1 1 0I2I2 1 I3I3

58. 58 2-to-1 MUX

59. M ULTIPLEXERS 2-to-1 MUX or 2 x 1 MUX 4-to-1 MUX MUX Y S Y I0I1 I2I3I0I1 I2I3 S 1 S 0 I0I1I0I1

60. M ULTIPLEXERS Quad 2-to-1 MUX MUX Y0 I0I1I0I1 S MUX Y1 I0I1I0I1 S MUX Y2 I0I1I0I1 S MUX Y3 I0I1I0I1 S A0A1A2A3 A0A1A2A3 B0B1B2B3 B0B1B2B3 S MUX A0A1 A2A3A0A1 A2A3 S E Y3Y2 Y1Y0Y3Y2 Y1Y0 B0B1 B2B3B0B1 B2B3 (two 4-bits input, one 4-bits output)

62. I MPLEMENTATION U SING M ULTIPLEXERS MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 x y zF 0 0 00 0 0 11 0 1 01 0 1 10 1 0 00 1 0 10 1 1 01 1 1 11 Example F ( x, y, z ) = ∑(1, 2, 6, 7) x y F F = z z z F = 0 0 F = 1 1

63. MUX Y I0I1 I2I3I4I5 I6I7I0I1 I2I3I4I5 I6I7 S 2 S 1 S 0 I MPLEMENTATION U SING M ULTIPLEXERS A B C DF 0 0 0 0 0 0 11 0 0 1 00 0 0 1 11 0 1 0 01 0 1 0 0 1 1 00 0 1 1 10 1 0 0 00 1 0 0 10 1 0 0 1 0 1 11 1 1 0 01 1 1 0 11 1 1 1 01 1 1 1 Example F ( A, B, C, D ) = ∑(1, 3, 4, 11, 12, 13, 14, 15) A B C F F = D D D D F = 0 0 F = D F = 1 0 D 1 1

64. Y I0I1 I2I3I4I5 I6I7I0I1 I2I3I4I5 I6I7 S 2 S 1 S 0 M ULTIPLEXER E XPANSION 8-to-1 MUX using Dual 4-to-1 MUX & one 2x1 Mux MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 MUX Y I0I1I0I1 S 0 1

65. 65 / 65 D E M ULTIPLEXERS DeMUX I Y3Y2Y1Y0Y3Y2Y1Y0 S 1 S 0 Y 3 Y2Y2 Y1Y1 Y0Y0 0 000I 0 100I0 1 00I00 1 I000

66. D E M ULTIPLEXERS / D ECODERS BinaryDecoder I1I0E I1I0E Y0Y1 Y2Y3 Y0Y1 Y2Y3 EI 1 I 0 Y 3 Y 2 Y 1 Y 0 0x 0 0 10 0 0 0 1 10 10 0 1 0 11 00 1 0 0 11 1 0 0 0 DeMUX I Y0Y1Y2Y3Y0Y1Y2Y3 S 1 S 0 Y 3 Y2Y2 Y1Y1 Y0Y0 0 000I 0 100I0 1 00I00 1 I000

67. T HREE -S TATE G ATES Tri-State Buffer AY C C AY 0 xHi-Z 1 00 1 1 AY C

68. T HREE -S TATE G ATES Y=Y= A C B A if C = 1 B if C = 0 2-to-1 line mux

69. T HREE -S TATE G ATES I0I0 Y E S1S1 I1I1 I2I2 I3I3 BinaryDecoder I1I0E I1I0E Y3Y2 Y1Y0 Y3Y2 Y1Y0 S0S0 4-to-1 line mux

70. 70 T HE P ROBLEMS : 4.18, 4.20 ( A ), 4.21, 4.22, 4.25 4.28, 4.29, 4.31, 4.32 4.34, 4.35