1. ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark Faust @ PSU ECE

2. Syllabus Combinatorial Logic Circuits Truth Tables Logic Functions References

3. Lecture 6 Topics –Combinational Logic Circuits Graphic Symbols (IEEE and IEC) Switching Circuits Analyzing IC Logic Circuits Designing IC Logic Circuits Detailed Schematic Diagrams Using Equivalent Symbols 3

4. Combinational Logic Circuits Combinational Logic –Outputs depend only upon the current inputs (not previous “state”) Positive Logic –High voltage (H) represents logic 1 (“True”) –“Signal BusGrant is asserted High” Negative Logic –Low voltage (L) represents logic 1 (“True”) –“Signal BusRequest# is asserted Low” 4

5. IEEE: Institute of Electrical and Electronics Engineers IEC: International Electro- technical Commission 5

6. n.o. = normally open n.c. = normally closed 6

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14. All Possible Two Variable Functions Question: How many unique functions of two variables are there? Recall earlier question… 14

15. Truth Tables B 5 B 4 B 3 B 2 B 1 B 0 F 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0. 1 1 1 1 1 1 1 0 1 2 3. 63 2 6 = 64 Question: How many rows are there in a truth table for n variables? As many rows as unique combinations of inputs Enumerate by counting in binary 2n2n 15

16. Two Variable Functions Question: How many unique combinations of 2 n bits? Enumerate by counting in binary 2 2 n 2 64 16 B 5 B 4 B 3 B 2 B 1 B 0 F 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0. 1 1 1 1 1 1 1 0 1 2 3. 63 2 6 = 64

17. All Possible Two Variable Functions Question: How many unique functions of two variables are there? B 1 B 0 F 0 0 0 0 1 1 1 0 1 1 1 0 2 2 = 4 rows 4 bits Number of unique 4 bit words = 2 4 = 16 17

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19. Analyzing Logic Circuits Reference Designators (“Instances”) X + Z X X + Y (X + Y)  (X + Z) 19

20. Analyzing Logic Circuits C ABAB BCBC A  B + B  C 20

21. Designing Logic Circuits F1 = A  B  C + B  C + A  B SOP form with 3 terms  3 input OR gate 21

22. Designing Logic Circuits F1 = A  B  C + B  C + A  B Complement already available 22

23. Some Terminology F1 = A  B  C + B  C + A  B Signal line – any “wire” to a gate input or output 23

24. Some Terminology F1 = A  B  C + B  C + A  B Net – collection of signal lines which are connected 24

25. Some Terminology F1 = A  B  C + B  C + A  B Fan-out – Number of inputs an IC output is driving Fan-out of 2 25

26. Some Terminology F1 = A  B  C + B  C + A  B Fan-in – Number of inputs to a gate Fan-in of 3 26

27. Vertical Layout Scheme – SOP Form 27

28. Vertical Layout Scheme – SOP Form 28

29. >2 Input OR Gates Not Available for all IC Technologies Solution: “Cascading” gates 29

30. Vertical Layout Scheme – POS Form F2 = (X+Y)  X+Y)  X+Z) 30

31. Designing Using DeMorgan Equivalents Often prefer NAND/NOR to AND/OR when using real ICs –NAND/NOR typically have more fan-in –NAND/NOR “functionally complete” –NAND/NOR usually faster than AND/OR 31

32. AND/OR forms of NAND DeMorgan’s Theorem 32

33. Summary of AND/OR forms Change OR to AND “Complement” bubbles 33

34. Equivalent Signal Lines 34

35. NAND/NAND Example 35

36. NOR/NOR Example 36

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