1. Counters Transition Tables Moore Outputs Counter Timing
ECEn/CS 224

2. General Sequential Systems
Current State
State Memory
Next State
Input Forming Logic
D Q
D Q
The current state loads the next state values in response to the clock edge.
IFL reacts after some gate delays to produce a new next state.
CLK
Current State 00 01 10 11 00
Next State 01 10 11 00 01
ECEn/CS 224

3. Transition Table for 2-Bit Counter
It is the truth table for the input forming logic…
It describes what the next state values are as a function
of the current state
(clock is assumed)
ECEn/CS 224

4. Implementation of 2-Bit CounterQ0 Q1
D Q
CLK N1 N0
N0 =Q0’
N1 =Q1⊕Q0
ECEn/CS 224

5. Example 2 – A Gray Code CounterQ1
D Q Q0
CLK N1 N0
N1= Q0
Ordering of TT rows chosen to make it easier to see the count pattern.
It doesn’t change result.
N0 = Q1’
ECEn/CS 224

6. Example 3 – Not All Count Values Used
Desired count sequence = 00 – 01 – …
What should next state for 10 be?
ECEn/CS 224

7. Example 3 – Not All Count Values Used
N1 = Q0
N0 = Q0’•Q1’
Do the normal KMap w/don’t cares minimization…
ECEn/CS 224

8. Example 4 – A Ring Counter
Desired count sequence = 001 – 010 – …
Doing KMaps leads to:
N2 = Q1
N1 = Q0
N0 = Q2
No big surprise here!!!!!
ECEn/CS 224

9. Example 4 – A Ring Counter
D Q Q2
D Q Q1
D Q Q0
CLK
ECEn/CS 224

10. General Counter Design Procedure
Write transition table for counter
Use X’s as appropriate
Reduce each Nx variable to an equation
Implement input forming logic (IFL) using gates
Draw schematic using FF’s + IFL
ECEn/CS 224

11. Counters With Alternative FF’s
Current State
State Memory
Next State
Input Forming Logic
T Q
ECEn/CS 224

12. Excitation Table for T Flip Flop
Transition Table
Excitation Table
Rearranging rows and/or columns…
Tells how inputs affect output
Tells what input to apply to achieve desired output transition
In the end, they are the same table, just rearranged…
ECEn/CS 224

13. TFF Counter Design Using Augmented Transition Table
T2 = Q1•Q0 T1 = Q0 T0 = ‘1’
Next state values
Inputs to apply to achieve desired next state
ECEn/CS 224

14. TFF Counter Design
T Q Q2
CLK
T Q Q1
CLK
‘1’
T Q Q0
CLK
ECEn/CS 224

15. Excitation Table for JK Flip Flop
Rearranging rows and/or columns…
Tells what inputs to apply to achieve desired output transition
Do you see why the X’s?
Tells how inputs affect output
In the end, they are the same table, just rearranged…
ECEn/CS 224

16. JKFF Gray Code Counter Design
J2 = Q1Q0’ K2 = Q1’Q0’
J1 = Q2’Q0 K1 = Q2Q0
J0 = Q2Q1 + Q2’Q1’ = K0’ K0 = Q2’Q1 + Q2Q1’ = Q2 © Q1
Next state values
Inputs to apply to achieve desired next state
ECEn/CS 224

17. General Counter Design Procedure
Write transition table for counter
Use X’s as appropriate
If not DFF’s, augment table
Reduce each FF input variable to equation
Implement IFL with gates
Draw schematic using FF’s + gates
ECEn/CS 224

18. Outputs = f(CurrentState)
Counters With Outputs
Outputs
D Q
Current State
Input Forming Logic
Next State
State Memory
Output Forming Logic
Outputs = f(CurrentState)
ECEn/CS 224

19. Counters With Outputs Z=1 when count={0,3,6}
Z is called a Moore or static output. It is a function only of the current state
ECEn/CS 224

20. Combined Transition Table
Current state
Next state
Output
Z = Q2’Q1’Q0’ + Q2’Q1Q0 + Q2Q1Q0’
(implement OFL with gates)
ECEn/CS 224

21. Counter Delay Characteristics
tsetup
tIFL Q0 Q1
D Q
CLK N1 N0
tCLK-Q
CLK
Current State (Q’s) 00 01 10
Next State (N’s) 01 10
TClockPeriod
TClockPeriod >= tCLK-Q + tIFL + tsetup
ECEn/CS 224

22. Counter Delay Example tCLK-Q = 1ns tIFL = 7ns tsetup = 2ns
TClockPeriod >= 10ns ( 10 x 10-9 sec)
ClockRate <= 100MHz (100 x 106 Hz)
Rate = 1/Period
ECEn/CS 224

23. Next State and Output Timings
tOFL
tOFL
tCLK-Q
tCLK-Q
More outputs appear tCLK-Q + tOFL after the clock edge.
CLK
Current State
010
011
100 Z
ECEn/CS 224

24. Counters and Timing The count sequence affects the size of IFL
The size of the IFL affects tIFL
tIFL affects TClockPeriod
Choosing binary counts is not always fastest or smallest
ECEn/CS 224

25. Example Problem Design a 3-bit binary counter
The Z output is TRUE iff count value is even
The Y output is TRUE iff count value is multiple of 3
ECEn/CS 224