1. Academy High Density FPGAs High Density FPGAs

2. Academy High Density FPGAs -2 Xilinx High Density FPGA Families n XC4000EX n XC4000XL n XC4000XV n Virtex

3. Academy High Density FPGAs -3 High Density FPGAs n Same Basic Architecture as 4KE (Spartan) n New Fabrication Process –New Power Supplies n More Logic –More Logic Cells and I/O Pins –New Packages n Architectural Enhancements –Better Routing, I/O

4. Academy High Density FPGAs -4 XC4000 Series FPGA Architecture

5. Academy High Density FPGAs -5 Simplified 4K CLB

6. Academy High Density FPGAs -6 Simplified Virtex CLB n 4 Logic Cells per CLB n Carry logic (2 independent chains) n 4 FFs/Latches, 2 BUFTs per CLB n 16 bits of SelectRAM per LUT (single / dual-port) LUT CARRY D CE SET RES Q DFF/LATCH LUT CARRY D CE SE T RES Q DFF/LATCH LUT CARRY D CE SET RES Q DFF/LATCH LUT CARRY D CE SE T RES Q DFF/LATCH

7. Academy High Density FPGAs -7 High Density FPGAs Use New Silicon Technology

8. Academy High Density FPGAs -8 0 0.2 0.4 0.6 0.8 1 1.2 1990199219941996199820002002 Year Feature Size (  ) Xilinx CMOS Process Technology Roadmap Xilinx’ fab partners use FPGAs to drive process 5V 3.3V 2.5V 1.8V 1.3V

9. Academy High Density FPGAs -9 New Fabrication Process 0.5um Process0.25um UMC Process XC4000EX XC4000XV/Virtex

10. Academy High Density FPGAs -10 High Density FPGAs are Faster

11. Academy High Density FPGAs -11 High Density ASIC Designs System Frequency 0 2 4 6 8 10 12 14 16 0-10 20-30 30-4040-5050-6060-7070-80 80-90 90-100 100-150150-200 >200 Average Clock Speed (MHz) Percentage of Designs Dataquest 1997 ASIC Design Starts by Average Clock Speed The High FPGA Density Arena

12. Academy High Density FPGAs -12 High Density FPGAs Have More Logic

13. Academy High Density FPGAs -13 High Density Arena Covers ASIC Designs Up To 250,000 Gates 0 5 10 15 20 25 30 <10K10-25K25-50K50-100K100- 150K 150- 250K >250K Design Size (gates) Percentage of Designs Dataquest 1997 Gate Array Design Starts by Gate Count The High Density Arena

14. Academy High Density FPGAs -14 High Density FPGAs Require New Power Supplies

15. Academy High Density FPGAs -15 0.35/0.25  FPGA, 5 Volt Compatible I/O n XL/XV accept 5 volt TTL inputs n XL/XV drive standard LVTTL levels n XV has separate I/O & Core Supplies XC4000E 5V Core 5V I/O XC4000XV 2.5V Core 3.3V I/O XC4000XL 3.3V Core 3.3V I/O 5V 3.3V 2.5V 5V 3.3V I/O Supply Core Supply Meets TTL Levels

16. Academy High Density FPGAs -16 High Density FPGAs Require new Packages

17. Academy High Density FPGAs -17 n First to use PQFP & VQFP n First to use BGA & SBGA (Super BGA) n Investigating flip-chip today for higher integration solutions 100 1000 199219941996199820002002 3000 PQFPs & VQFPs BGA Flip-chip SBGA Xilinx Pioneers FPGA Packages Package Pins Year

18. Academy High Density FPGAs -18 High Density FPGAs Have Increased Routing n Most of the silicon area is used for interconnect

19. Academy High Density FPGAs -19 High Density FPGAs Require More Interconnect n Larger designs require more and longer interconnects n Large designs preclude hand placement n More interconnect resources enable higher performance designs –Interconnect delay dominates path –50% - 80% of total path delay n More interconnect enables faster routing

20. Academy High Density FPGAs -20 XC4000X Interconnect Hierarchy

21. Academy High Density FPGAs -21 Virtex Interconnect n 4 LCs per CLB n Fast local routing within CLBs n General purpose routing between CLBs n Hierarchical interconnect is scaleable, and has predictable fast performance

22. Academy High Density FPGAs -22 High Density FPGAs Have Clock Distribution Enhancements n EX/XL/XV –8 Global Low Skew Clock Buffers - BUFGLS (for Logic) –8 Global Early Clock Buffers BUFGE (for I/O) n Virtex –Very Low Skew Clock Buffers –On-Chip DLL to remove clock delay

23. Academy High Density FPGAs -23 XC4000X Global Early Buffers Left and Right (#1 shown)Top and Bottom (#8 shown)

24. Academy High Density FPGAs -24 XC4000X: Faster Clock-to-Out n Use of BUFGE #1,2,5,6 allows reduction of clock to out delay by up to 2-3ns for XC4085XL-09 –Tgls(XC4085) = 5.5ns Tickof = 9.0ns –Tge(from TRCE) = 2.8ns Tickeof = 6.3ns BUFGLS BUFGE Data to internal logic PAD Clock PAD FF D Q > OFD D Q > CLB IOB 5.5ns 2.8ns 2.8ns+3.5ns

25. Academy High Density FPGAs -25 Virtex Clocking and PLL n Ultra-low skew, fast clocks –66 MHz PCI performance without PLL n Phase-Locked Loop (PLL) –Compensate for clock network delay –Clock multiplication –Duty cycle correction –Reference output for system timing

26. Academy High Density FPGAs -26 High Density FPGAs Have IOB Enhancements n EX/XL/XV –Fast Capture Latch (FCL) in IOB –Output Multiplexer (OMUX) in IOB n Virtex –Registered Output Enable –Support for non-TTL Signaling

27. XC4000EX/XL/XV IOB

28. Academy High Density FPGAs -28 XC4000X Fast Capture Latch n Additional latch on input driven by output’s clock signal n Allows capture of input by very fast clock –Followed by standard I/O storage element for synchronization to internal logic BUFGE BUFGLS Data to internal logic ILFFX PAD Clock PAD FCL D Q G IFD D Q >

29. Academy High Density FPGAs -29 Virtex IOB n Fast I/O drivers n Registered input, output, 3-state enable control n Programmable slew rate, pull-up, input delay, etc. D CE S/R Q DFF/LATCH D CE S/R Q DFF/LATCH D CE S/R Q DFF/LATCH PAD

30. Academy High Density FPGAs -30 High Density FPGAs Need more RAM n Hierarchy of RAM –Registers –Distributed SRAM (in 4K CLB) –Block RAM (Virtex Only) –External RAM SDRAM, SDRAM FIFOs (First In First Out Memories) –System RAM (Via PCI BUS)

31. Academy High Density FPGAs -31 4KE/X Single-Port RAM

32. Academy High Density FPGAs -32 4K E/X Dual-Port RAM

33. Academy High Density FPGAs -33 Virtex Block RAM n Configure as: 4096 bits with variable aspect ratio n 8-30 blocks per device (20K-200K logic gate devices) n True dual-port, fully synchronous operation –Cycle time <10 ns n Flexible block RAM configuration –5 blocks: 2K x 10 video line buffer –1 block: 512 x 8 ATM buffer (9 frames) –4 blocks: 2K x 8 FIFO –9 blocks: 4K x 9 FIFO with parity WEA ENA CLKA ADDRA DINA DOA DOB RAMB4 WEB ENB CLKB ADDRB DINB

34. Academy High Density FPGAs -34 High Density FPGAs have Increased Complexity n Bigger Designs n Simulation/Error analysis is more difficult n New functions in FPGAs –DSP type Functions –Data Processing Functions –Memory –CPUs

35. Academy High Density FPGAs -35 High Density FPGAs have new design entry methods n ASIC toolkit –Verilog / VHDL design entry n Logic is purchased and Integrated as LogicCores (example PCI) –Integration / Modification still required –Simulation and Verification required n Software algorithm/program may be source of design

36. Academy High Density FPGAs -36 New Problems when using High Density FPGAs n New Tools –M1 is required for for EX/XL/XV n Tools are slower for bigger FPGAs n Power must be managed –Can’t be ignored any longer –Heatsinks, Fans may be necessary n Parts are physically bigger and have more pins such as the BG560 package n BGA Packages require higher tech FAB

37. Academy High Density FPGAs -37 Team Design n Typical Productivity is 10K gates/month n 250K design will take over 2 years !!! n A Single High Density FPGA Design may require a team of designers. n FPGA designers need same skills and tools as ASIC and SW designers. n Board and System level simulation may be required

38. Academy High Density FPGAs -38 Web Resources –Crossroads http://web/ http://web/ –Site Search http://web:7000/cgi-bin/search.cgi/x-catalog:/web:7000/Crossroads http://web:7000/cgi-bin/search.cgi/x-catalog:/web:7000/Crossroads –FTP site ftp://ftp.xilinx.com/pub/ ftp://ftp.xilinx.com/pub/ –High Density Marketing Home page http://web/corpmktg/whoswho/dsfpga.htm http://web/corpmktg/whoswho/dsfpga.htm –Marketing Presentations http://web/corpmktg/custpres/http://web/corpmktg/custpres/ –FAE Newsgroup news:xilinx.fae.questions news:xilinx.fae.questions

39. Academy High Density FPGAs -39 Collateral Resources –Datasheets http://www.xilinx.com/partinfo/db96.htm http://www.xilinx.com/partinfo/db96.htm –Application Notes http://www.Xilinx.com/apps/appsweb.htm http://www.Xilinx.com/apps/appsweb.htm –Speed Files ftp://ftp.xilinx.com/pub/swhelp/speed_files/ ftp://ftp.xilinx.com/pub/swhelp/speed_files/ –BSDL(Boundary Scan) http://www.xilinx.com/support/techsup/ftp/htm_index/sw_bsdl.htm http://www.xilinx.com/support/techsup/ftp/htm_index/sw_bsdl.htm –IBIS Models(I/O Characteristics) ftp://ftp.xilinx.com/pub/swhelp/ibis/ ftp://ftp.xilinx.com/pub/swhelp/ibis/ –Engineering Presentations http://web:80/corpcomm/distribution/engineer.htm http://web:80/corpcomm/distribution/engineer.htm –High Density Product Availability Guide http://web/corpmktg/home/psu/xc4000ex/4kexsil.htm http://web/corpmktg/home/psu/xc4000ex/4kexsil.htm

40. Academy High Density FPGAs -40 Technical Data Sources –Product availability http://web/corpmktg/home/psu/newpsu.htm http://web/corpmktg/home/psu/newpsu.htm –Competitive Benchmark Server http://icarus/cgi-bin/getmag2http://icarus/cgi-bin/getmag2 –Lab Reports http://web/~yiding/fpgalab/labreports/labreports.htmlhttp://web/~yiding/fpgalab/labreports/labreports.html –Packaging Data http://web/aprfa/pkg/index.htm http://web/aprfa/pkg/index.htm –The Pinout Page http://web/prodtech/pins/index.html http://web/prodtech/pins/index.html –The Software Page http://web/randd/software/ http://web/randd/software/

41. Academy High Density FPGAs -41 High Density Marketing n XL/XV Marketing –David Squires –Barry Chaffin –Andrew Girardi n Virtex Marketing –Bruce Jorgens n Applications Engineering –Al Graf –Brad Taylor http://web/~blt/ http://web/~blt/ –Hernan Saab

42. Academy High Density FPGAs -42 High Density Performance Estimation n Need to Know –Design Size - 4LUTS or Gates or Registers –I/O pins - Number of pins, Speed –Target System Frequency –Power Requirements –Memory Requirements

43. Academy High Density FPGAs -43 Capacity n 1 Logic Cell = 1 Input LUT+ 1 Register + Carry n 1 Logic Cell = 8-25 system gates

44. Academy High Density FPGAs -44 I/O Pins

45. Academy High Density FPGAs -45 Typical Power/FPGA n Based on App Brief #XBRF014 http://www.xilinx.com/xbrf/xbrf014.pd http://www.xilinx.com/xbrf/xbrf014.pd n Frequency = 50 MHZ, 70% Fill,@ 15% toggle rate, n 100% of I/O Pins@ 25% I/O toggle rate n 50pf I/O Loading

46. Academy High Density FPGAs -46 Peak Power could be 4X Typical Power –50 MHz -> 100 MHz, – 70% Fill -> 100%, – 15% toggle rate -> 100%toggle rate, –100% of I/O Pins –pin 25% toggle rate -> 100% toggle rate

47. Academy High Density FPGAs -47 Internal FPGA Speed

48. Academy High Density FPGAs -48 Application Speed n FPGA Speed depends on FPGA application and design methodology

49. Academy High Density FPGAs -49 FPGA Components n Basic Classes of Components –I/O pins –Interconnect –Combinatorial Circuits State Machines Multiplexers AND/OR terms –Math Circuits –Memories

50. Academy High Density FPGAs -50 I/O Frequency n Fio(ext) = Maximum I/O Clock frequency n Fio(ext) = 1/(Tckout+ Tsetup) –Full delay inputs (0ns hold) –Fast outputs –Pin to Pin (referenced to external clock pin) FPGA1 FFO D Q > PAD IFF D Q > PAD External Clock External DATA Internal Clock 2 Internal Clock 1 DoutDin

51. Academy High Density FPGAs -51 I/O Speed

52. Academy High Density FPGAs -52 Interconnect Test Pattern (XC4085)

53. Academy High Density FPGAs -53 Interconnect Performance

54. Academy High Density FPGAs -54 Elemental FPGA Circuit n 1 LUT + 1 net + 1 Register n Fmax = 1/( Tcko + Tnet + Tick) n Fmax = 1/(1.6ns + 12.5ns + 0.9ns); n Fmax =66Mhz FF D Q > FF D Q > 4LUT CLK Tcomp = Tcko + Tnet + Tcki ; Net

55. Academy High Density FPGAs -55 Combinatorial Circuits n N LUTs (Look Up Tables) between Registers n Each LUT adds 1 LUT delay + 1 Net delay n Tcom = Tcko+N*(Tnet+Tlut); net FF 4LUT net

56. Academy High Density FPGAs -56 State Machines n Characterized by number of Logic Levels n 1 Hot encoded typically 1-3 Levels of 4LUTS n Non 1 Hot typically 3-6 LUT levels n Typically some non local interconnect n State Machines Limit System Frequency

57. Academy High Density FPGAs -57 Performance vs Logic Level

58. Academy High Density FPGAs -58 64 input combinatorial circuit XC4000XL-1 n 32 Bit Equality Comparator n 64 Bit AND/OR Term n 16:1 Multiplexer in same logic depth net FF 2LUT 4LUT net 4LUT 3LUT 4LUT FF \4\4 \4\4 \4\4 … 4LUT 3LUT FF 64 Signals8 Signals1 Signal

59. Academy High Density FPGAs -59 Multiplexer Performance

60. Academy High Density FPGAs -60 And-Term Performance

61. Academy High Density FPGAs -61 Math Components n Adders/Subtractors n Counters n Magnitude Comparators n Multipliers/Dividers n Max/Min (sorters)

62. Academy High Density FPGAs -62 Carry Chain n Carry Chain is speed limit n Tadd(N)= Tcko +Tnet+Tlut+(N-2)/2*Tbyp+Tick – N=number of bits in adder FF D Q > FF D Q > Carry 4LUT Carry 4LUT C0C1C2 Net Carry chain of a 4 Bit ripple carry adder. sum d

63. Academy High Density FPGAs -63 Cascaded Adders n Each Cascaded adder adds two LUT delays + Net delay To Tadd n Tadd(M) = Tadd1 + (M-1)*(2*Tlut+Tnet) –M = Number of cascaded stages 3 cascaded adders sum=a+b+c+d; AD D FF D Q > FF D Q > AD D FF D Q > FF D Q > FF D Q > b a c d sum

64. Academy High Density FPGAs -64 Adder Performance

65. Academy High Density FPGAs -65 RAMs n Often the Limiting Factor in circuits n Register Files n Delay elements n FIFOs n Microcode Storage

66. Academy High Density FPGAs -66 XL Dual Port RAM Circuit FF D Q > Dual Port RAM Circuit FF D Q > FF D Q > FF D Q > DPRAM Dw Dr Awr Ard We > wdata waddr rdata raddr clock MUX netwrite_data read_address write_enable write_address

67. Academy High Density FPGAs -67 XL-09 Dual-Port Ram Performance n 16-Bit deep = 133MHz read/write n 32-Bit to 1024-Bit deep = 133MHz write n 32-Bit to 1024-Bit deep = 133MHz – Pipelined read n 128-Bit = 75MHz –Non pipelined read