1. Reconfigurable Computing - Designing and Testing John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound, Western Australia

2. FPGA Architectures  Design Flow  Good engineering practice requires that design exercises should follow a defined procedure  User’s specification  This is your starting point  It may take several forms 1.Informal requirements given to you by your user / client / … 2.Formal written requirements All functional and non-functional requirements are precisely stated Sometimes resulting in a very large (and dull) document! 3.Something in between Your tutorial assignment was in this category Mostly formal, but with some gaps you would need to fill in Using research / further discussion with client / … etc

3. Step 1 - Analysis  Design Step 1 – Analyze specification  Identify suitable circuit modules by carefully reading specification  Start at top level – identify major components first  In particular, identify interfaces between environment and device that you’re designing Washing machine example: Inputs - User buttons, dials, sensors, … Outputs – Motors, indicator lights, audio, …  From these, specify the top-level entity ENTITY wm IS start, lid, stop : IN std_logic_vector; audio : OUT audio_sample; … END ENTITY wm;

4. Step 1 - Analysis  Design Step 1 – Analyze specification  Note that you may defer implementation details!  In this case, you don’t want to bother with the details of the audio output stream yet, so just specify a type audio_sample without filling in details for it yet.  Checking your design  A VHDL compiler (usually the simulator’s compiler) should be used to check completeness and consistency of a design from the early stages! ENTITY wm IS start, lid, stop : IN std_logic_vector; audio : OUT audio_sample; … END ENTITY wm;

5. Step 1 – Analysis : Checking the Design  Design Step 1 – Analyze specification  Checking your design  A VHDL compiler (usually the simulator’s compiler) should be used to check completeness and consistency of a design from the early stages!  Even though many details are missing Initially you may have no architecture blocks at all!  A compiler will warn you of missing, incomplete or inconsistent specifications  Thus although diagrams (and other informal modeling tools – like pencil and eraser!) are very useful, you should be generating formal (checkable) design specifications at a very early stage. These may be abstract High level Missing implementation details ‬but they are vital for detecting design errors!

6. Step 1 – Analysis : Checking the Design  Design Step 1 – Analyze specification  Checking your design  In this example, you have deliberately deferred a decision about the exact form of audio_sample.  You will need to provide a definition of it for the compiler, but you can substitute anything that the compiler will accept at this stage!  Make a package ENTITY wm IS start, lid, stop : IN std_logic_vector; audio : OUT audio_sample; … END ENTITY wm; PACKAGE audio IS TYPE audio_sample IS integer RANGE 0 TO 255; END PACKAGE audio;

7. Step 1 – Analysis : Checking the Design  Design Step 1 – Analyze specification  Deferred detail...  Many possibilities exist for the deferred detail … or PACKAGE audio IS TYPE audio_sample IS std_logic_vector(0 TO 7); END PACKAGE audio; PACKAGE audio IS TYPE audio_sample IS std_logic_vector(sample_size); END PACKAGE audio; PACKAGE audio IS TYPE audio_sample IS …; -- Your own idea! END PACKAGE audio; Key idea: Use the compiler to check your design as much as possible! These deferred definitions are necessary to avoid messages like ‘xxx is undefined’ which prevent the compiler from checking the rest of the design!

8. Step 2 - Refining the design  Once you have a formal VHDL specification for the high level entity for your design  Step 2 is to refine the design wm (washing controller) start lid motor stop valves audio

9. Step 2 - Refining the design  Step 2 is to refine the design  Determine the internal structure of your component  What entities do we need to implement the requirements? Counters, timers, … State machines, … (overall control) Device controllers eg PWM for motors, display controllers, …  Write formal models (VHDL entities) for each internal component ENTITY count_down_timer IS PORT( clk, reset : IN std_logic; cycles : IN std_logic_vector; complete : OUT std_logic ); END ENTITY count_down_timer; ENTITY speech_synth IS PORT( … ); END ENTITY speech_synth; ENTITY motor_control IS PORT( … ); END ENTITY motor_control;

10. Step 2 - Refining the design  Step 2 is to refine the design  Determine the internal structure of your component  Write formal models (VHDL entities) for each internal component  Determine how these models are connected wm (washing controller) start lid motorstop valves audio main_fsm speech_synth c_d_timer

11. Step 4 – Assemble the system  Step 4 – Build a model which includes all the components of the system you are building ie write the ARCHITECTURE block  Generally this will be a structural VHDL model  VHDL models may be mixed, so this is not a hard rule! start lid motor stop valves wm (washing controller) audio main_fsm speech_synth c_d_timer ARCHITECTURE a OF wm IS COMPONENT main_fsm PORT( … ); COMPONENT speech_synth PORT( … ); COMPONENT c_d_timer PORT( … ); SIGNAL … BEGIN fsm: main_fsm PORT MAP( … ); t1: c_d_timer PORT MAP( … ); END ARCHITECTURE a;

12. Step 5 – Check the design  Use the compiler (simulator or synthesizer) to check the design  Check for  Completeness All required modules are present All required signals are present  Consistency All signals are connected to signals of matching types ‬ eg No std_logic connected to std_logic_vector std_logic_vector sizes are compatible (no 8-bit busses connected to 16-bit ones!) ‬ etc  For example, checking the models sketched in the last few slides would reveal that there was no clock to feed the timer!  So one would be added …  Repeat steps 1 – 5 until no errors are reported  Even though some types ( eg audio_sample ) are not in their final form!

13. Step 6 – Complete the details  Fill in all architectures  You only need top-level structural architectures to check the design!  Now you need to complete them all!  Decide on all deferred types  Any design decision that you deferred …  Add assertions!  Don’t forget to try to make your design check itself

14. Step 7 - Simulation  Now we’re going to check the design using the simulator  We built a model of the device we’re going to place in an FPGA (or ASIC or …) wm (washing controller) audio main_fsm speech_synth c_d_timer motor valves start lid pause clock Note that the clock has been added now! (We discovered that it was missing in design check!)

15. Modern Programmable Logic  As technology has evolved, so have programmable devices  Today’s FPGAs contain  Millions of ‘gates’  Memory  Support for several I/O protocols - TTL, LVDS, GTL, …  Arithmetic units - adders, multipliers  Processor cores

16. FPGA Architecture  The ‘core’ architecture of most modern FPGAs consists of  Logic blocks  Interconnection resources  I/O blocks

17. Typical FPGA Architecture  Logic blocks embedded in a ‘sea’ of connection resources  CLB = logic block IOB = I/O buffer PSM = programmable switch matrix This particular arrangement is similar to that in Xilinx 4000 (and onwards) chips - devices from other manufacturers are similar in overall structure

18. Logic Blocks  Combination of  And-or array or Look-Up-Table (LUT)  Flip-flops  Multiplexors  General aim  Arbitrary boolean function of several variables  Storage  Designers try to estimate what combination of resources will produce the most efficient application  circuit mappings Xilinx 4000 (and on) CLB 3 LUT blocks 2 Flip-Flops (Asynch Reset) Multiplexors Clock / Reset Lines

19. Adders  Adders appear in most designs  Arithmetic Adders (including subtracters)  Other arithmetic operators  eg multipliers, dividers  Counters (including program counters in processors)  Incrementors, decrementors, etc  They also often appear on the critical path  Adder performance can be crucial for system performance  Because of their importance, researchers are still searching for better ways to add!  Adder structures proposed already  Ripple carry  Carry select  Carry skip  Carry look-ahead  Manchester  … and several dozen more variants

20. Ripple Carry Adder  The simplest and most well known adder  How long does it take an n -bit adder to produce a result?  n x propagation delay( FA: (a or b)  carry )  We can do better than this - using one of many known better structures  but  What are the advantages of a ripple carry adder?  Small  Regular  Fits easily into a 2-D layout! FA a1a1 b1b1 c in c out s1s1 FA a0a0 b0b0 c in c out s0s0 FA a n-1 b n-1 c in c out s n-1 FA a n-2 b n-2 c in c out s n-2 carry out Very important in packing circuitry into fixed 2-D layout of an FPGA!

21. Ripple Carry Adders  Ripple carry adder performance is limited by propagation of carries FA a1a1 b1b1 c in c out s1s1 FA a0a0 b0b0 c in c out s0s0 FA a n-1 b n-1 c in c out s n-1 FA a n-2 b n-2 c in c out s n-2 carry out FA a3a3 b3b3 c in c out s3s3 FA a2a2 b2b2 c in c out s2s2 On an FPGA, this link is often the major source of time delay … because one or two FA blocks will often fit in a logic block! LB Connections within a logic block are fast! Connections between logic blocks are slower

22. ‘Fast Carry’ Logic  Critical delay  Transmission of carry out from one logic block to the next  Solution (most modern FPGAs)  ‘Fast carry’ logic  Special paths between logic blocks used specifically for carry out  Very fast ripple carry adders!  More sophisticated adders?  Carry select  Uses ripple carry blocks - so can use fast carry logic  Should be faster for wide datapaths?  Carry lookahead  Uses large amounts of logic and multiple logic blocks  Hard to make it faster for small adders!

23. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry Here we build an 8-bit adder from 4-bit blocks ‘Standard’ n -bit ripple carry adders n = any suitable value

24. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry After 4*t pd it will produce a carry out This block adds the 4 low order bits These two blocks ‘speculate’ on the value of cout 3 One assumes it will be 0 the other assumes 1

25. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry After 4*t pd it will produce a carry out This block adds the 4 low order bits After 4* tpd we will have: sum 0-3 (final sum bits) cout 3 (from low order block) sum0 4-7 cout0 7 (from block assuming 0 c in ) sum1 4-7 cout1 7 (from block assuming 1 c in )

26. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry Cout 3 selects correct sum 4-7 and carry out All 8 bits + carry are available after 4*t pd (FA) + t pd (multiplexor)

27. Carry Select Adder  This scheme can be generalized to any number of bits  Select a suitable block size ( eg 4, 8)  Replicate all blocks except the first  One with c in = 0  One with c in = 1  Use final c out from preceding block to select correct set of outputs for current block

28. Fast Adders  Many other fast adder schemes have been proposed eg  Carry-skip  Manchester  Carry-save  Carry Look Ahead  If implementing an adder ( eg in programmable logic) do a little research first!

29. Fast Adders  Challenge: What style of adder is fastest / most compact for any FPGA technology?  Answer is not simple  For small adders ( n < ?), fast carry logic will certainly make a simple ripple carry adder fastest  It will also use the minimum resources - but will need to be laid out as a column or row  For larger adders ( ? < n < ? ), carry select styles are likely to be best -  They use ripple carry blocks efficiently  For very large adders ( n > ? ), a carry look ahead adder may be faster?  But it will use considerably more resources!

30. Exploiting a manufacturer’s fast carry logic  To use the Altera fast carry logic, write your adder like this: LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm ; USE lpm.lpm_components.all ; ENTITY adder IS PORT (c_in : IN STD_LOGIC ; a, b : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; sum : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; c_out : OUT STD_LOGIC ) ; END adderlpm ; ARCHITECTURE lpm_structure OF adder IS BEGIN instance: lpm_add_sub GENERIC MAP (LPM_WIDTH => 16) PORT MAP (cin => Cin, dataa => a, datab => b, result => sum, cout => c_out ) ; END lpm_structure ;

31. What about that carry in?  In an ALU, we usually need to do more than just add!  Subtractions are common also  Observe  c = a - b is equivalent to  c = a + (-b)  So we can use an adder for subtractions if we can negate the 2 nd operand  Negation in 2’s complement arithmetic?

32. Adder / Subtractor  Negation in 2’s complement arithmetic?  Rule:  Complement each bit  Add 1 eg BinaryDecimal 0001 1 Complement 1110 Add 1 1111 -1 0110 6 Complement 1001 Add 1 1010 -6

33. Adder / Subtractor  Using an adder  Complement each bit using an inverter  Use the carry in to add 1! a b carry c c in FA 0 1 add/ subtract

34. Example - Generate ENTITY adder IS GENERIC ( n : INTEGER := 16 ) ; PORT (c_in : IN std_ulogic ; a, b : IN std_ulogic_vector(n-1 DOWNTO 0) ; sum : OUT std_ulogic_vector(n-1 DOWNTO 0) ; c_out : OUT std_ulogic ) ; END adder; ARCHITECTURE rc_structure OF adder IS SIGNAL c : STD_LOGIC_VECTOR(1 TO n-1) ; COMPONENT fulladd PORT (c_in, x, y : IN std_ulogic ; s, c_out : OUT std_ulogic ) ; END COMPONENT ; BEGIN FA_0: fulladd PORT MAP ( c_in=>c_in, x=>a(0), y=>b(0), s=>sum(0), c_out=>c(1) ) ; G_1: FOR i IN 1 TO n-2 GENERATE FA_i: fulladd PORT MAP ( c(i), a(i), b(i), sum(i), c(i+1) ) ; END GENERATE ; FA_n: fulladd PORT MAP (C(n-1),A(n-1),B(n-1),Sum(n-1),Cout) ; END rc_structure ;

35. IEEE 1164 standard logic package  Bus pull-up and pull-down resistors can be ‘inserted’  Initialise a bus signal to ‘H’ or ‘L’:  ‘0’ or ‘1’ from any driver will override the weak ‘H’ or ‘L’: SIGNAL not_ready : std_logic := ‘H’; IF seek_finished = ‘1’ THEN not_ready <= ‘0’; END IF; /ready 10k V DD DeviceADeviceBDeviceC