1. ECE 511: Digital System & Microprocessor

2. Course Outline WeekSubject W1Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor Instruction Set & Programming W7-W9Memory Interfacing W10-W12Parallel I/O Interfacing

3. References J. L. Antonakos, “The 68000 Microprocessor: Hardware and Software Principles & Applications,” 5 th Ed., Pearson Prentice-Hall, 2004. C. M. Gilmore, “Microprocessors: Principles & Applications,” 2 nd Ed., McGraw-Hill, 1995. A. Clements, “Microprocessor System Design,” PWS-Kent, 1992.

4. Course Evaluation Tests x 230% Quizzes x 320% Mini Projects50%

5. If you have problems, please contact me: Ahmad Ihsan bin Mohd Yassin Rm. T2-A13-1A, Dept. of Comp. Eng. Faculty of Elect. Eng. UiTM, Shah Alam. 03-55436118, 017-2576295 *Please call before you see me.

6. Digital Logic Review: Part I ECE 511: Digital System & Microprocessor.

7. What we will learn in this session: Review of logic gates. Flip-flops. Decoders. Universal representation of logic gates.

8. Gates

9. What are gates? Gates are:  Simple electronic devices.  Constructed using transistors.  Used to design digital systems. Three Basic Gates:  AND  OR  NOT Basic Gates can be combined into Extended Gates. Usually packed into ICs.

10. Gates as Building Blocks

11. Basic Gate - AND The AND gate is similar to multiply operation. A AND B C A BC 0 1 0 1 0 0 1 1 0 0 0 1 TRUTH TABLE

12. Basic Gate - OR The OR gate is similar to add operation. OR A B C A BC 0 1 0 1 0 0 1 1 0 1 1 1 TRUTH TABLE

13. Basic Gate - NOT The NOT gate performs the inverse operation. NOT A B TRUTH TABLE A B 0 1 1 0

14. Extended Gates Combination of basic gates to perform complex functions:  NAND  NOR  XOR  XNOR  Flip-Flops

15. NAND Gate Adds NOT after AND gate. AND outputs are inverted  NAND (NOT-AND). A AND B C NOT A NAND B C A BC 0 1 0 1 0 0 1 1 1 1 1 0 TRUTH TABLE

16. NOR Gate Adds NOT after OR gate. OR outputs are inverted  NOR (NOT-OR). OR A B C NOT C NOR A B A BC 0 1 0 1 0 0 1 1 1 0 0 0 TRUTH TABLE

17. XOR Gate XOR performs the Exclusive Or operation. When A=B, C=0; when A≠B, C=1. A BC 0 1 0 1 0 0 1 1 0 1 1 0 TRUTH TABLE XOR A B C

18. XNOR Gate Adds NOT after XOR gate. XOR outputs inverted  XNOR (NOT XOR). A BC 0 1 0 1 0 0 1 1 1 0 0 1 TRUTH TABLE XOR A B C NOTXOR A B C

19. Flip-Flops

20. An extended gate used as memory:  Each FF stores 1 bit. 2 gates, feedback connections. 2 inputs, 2 outputs. More complex ones may:  Use timing from CLK.  Perform bit toggle.

21. Reset-Set (RS) Flip-Flop 4 states:  Three stable (Set, Reset, and Keep).  One not stable (Unused). 2 inputs, 2 outputs. May also contain clock (CLK) signal.

22. RS Flip-Flop *Assuming initial condition: S = 0, R = 0, Q = 0 Q prev SRQ N/A000 0101 1010 Doesn’t matter 11N/A Unstable KEEP: Output unchanged SET: Output set (Q = 1) RESET: Output reset (Q = 0) Q’ 1 0 1 N/A *As long as S=0 and R=0, Q will always remain at previous state. RSFF R S Q Q’

23. Clocked RS Flip-Flop *Assuming initial condition: S = 0, R = 0, Q = 0 Unstable KEEP: Output unchanged SET: Output set (Q = 1) RESET: Output reset (Q = 0) RSFF R S Q Q’ CLK Only active when CLK is ↑ Reduced sensitivity to noise. Q prev SRQ N/A000 0101 1010 Doesn’t matter 11N/A Q’ 1 0 1 N/A CLK ↑ ↑ ↑ ↑ 0 Doesn’t matter Doesn’t matter 01↓

24. JK Flip-Flop Same as RS, but forbidden state used to toggle bit. Can also be clocked using CLK. Q prev JKQ N/A000 0101 1010 Q 11Q Toggle Output unchanged Output set (Q = 1) Output reset (Q = 0) Q’ 1 0 1 Q *Assuming initial condition: J = 0, K = 0, Q = 0

25. JK Flip-Flop Q prev SRQ N/A000 0101 1010 Q 11Q Toggle Output unchanged Output set (Q = 1) Output reset (Q = 0) Q’ 1 0 1 Q J K Q Q *Assuming initial condition: J = 0, K = 0, Q = 0

26. Clocked JK Q prev SRQ N/A000 0101 1010 Q 11Q Toggle Output unchanged Output set (Q = 1) Output reset (Q = 0) CLK ↑ ↑ ↑ ↑ J K Q Q 0 Doesn’t matter Doesn’t matter 0↓ Only active when CLK is ↑ Reduced sensitivity to noise.

27. D-Flip-Flop Data latch. Modification of RSFF. Stores 1-bit of information.  Can be combined to store more. Data are stored in memory using millions of DFFs.

28. D-Flip-Flop Q prev DQ Doesn’t Matter 11 00 Output set (Q = 1) Output reset (Q = 0) Q’ 0 1 EN 1 1 *Only active when EN is 1 DFF D EN Q Q’ Q PREV Doesn’t Matter Q PREV Q’ PREV 0

29. D-Flip-Flop: Timing Diagram D EN Q

30. Storing 8-bits using DFF (RAM) DFF Q3Q5Q6Q7Q1Q2Q4Q0 EN D3D5D6D7D1D2D4D0 Data Bus

31. Asynchronous Latch Allows both synchronous & asynchronous operations:  Synchronous: CLK driven (Clocked JK).  Asynchronous: similar to RSFF. 5 inputs, 2 outputs:  J, K and CLK for synch. operation.  PR, CLR for asynch. operation.

32. Asynchronous Latch PRECLRQ 00Follows J, K, CLK (Synch. JK) 01Q = 0, resets output. 10Q = 1, sets output. 11Not valid. CLK J K Q Q CLR(R) PRE(S)

33. Universal Gates – NAND and NOR

34. NAND and NOR as Universal Gates In industry, NAND and NOR gates are most common. Reason?  Can be used to represent any gate (functionally complete).  Easiest & cheapest to produce.

35. NAND Logic

37. NOR Logic

39. IC 4011 IC 7402

40. Decoders

41. Decoder A digital circuit that detects a specific combination of input bits (code), and indicates the presence of the code by a specific output. Typically has n inputs and 2 n outputs, but other combinations also exist. However, the number of inputs is always less than the outputs (noInputs < noOutputs). Each combination of inputs will generate a unique pattern at the output.

42. Example: Active High 2-4 Decoder 2-4 Decoder I0I0 I1I1 Y0Y0 Y1Y1 Y2Y2 Y3Y3 1 0 0 0 0 1 0 0 0 0 1 0 Y0Y0 0 0 0 1 I0I0 0 1 0 1 I1I1 0 0 1 1 Y3Y3 Y2Y2 Y1Y1 A specific pattern at the inputs. Will activate a specific bit at the outputs.

43. Example: Active Low 2-4 Decoder 2-4 Decoder I0I0 I1I1 Y’ 0 Y’ 1 Y’ 2 Y’ 3 0 1 1 1 1 0 1 1 1 1 0 1 Y’ 0 1 1 1 0 I0I0 0 1 0 1 I1I1 0 0 1 1 Y’ 3 Y’ 2 Y’ 1 A specific pattern at the inputs. Will activate a specific bit at the outputs.

44. Example: Active High 3-8 Decoder 0 1 00 00 100 110 1 1 00 10 110 111 00000001 00000001 1 00 000 0000 00000 0000001 0 1 1 1 1 00000 00000 0000 0 000 0 0 0 ABCY7Y6Y5Y4Y3Y2Y1Y0

45. Example: Active Low 3-8 Decoder 0 1 00 00 100 110 1 1 00 10 110 111 11111110 11111110 0 11 111 1111 11111 1111110 1 0 0 0 0 11111 11111 1111 1 111 1 1 1 ABCY7’Y6’Y5’Y4’Y3’Y2’Y1’Y0’

46. Encoder vs. Decoder 8  3 Encoder I0I0 I7I7 I6I6 I5I5 I4I4 I3I3 I2I2 I1I1 I4I4 I5I5 I6I6 I7I7 Y0Y0 Y1Y1 Y2Y2 I0I0 I1I1 I2I2 I3I3 0 0 11 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0000 100 001 101 100 11 0 111 0 Y2Y2 Y0Y0 Y1Y1

47. Encoder vs. Decoder 3  8 Decoder I0I0 I7I7 I6I6 I5I5 I4I4 I3I3 I2I2 I1I1 Y2Y2 Y0Y0 Y1Y1 11 000 100 001 101 100 11 0 111 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 I4I4 I5I5 I6I6 I7I7 Y0Y0 Y1Y1 Y2Y2 I0I0 I1I1 I2I2 I3I3

48. What Goes on Inside a Decoder? Y0 Y1 Y2 I 0 = Y 0 Y 1 Y 2 I 2 = Y 0 Y 1 Y 2 I 3 = Y 0 Y 1 Y 2 I 4 = Y 0 Y 1 Y 2 I 5 = Y 0 Y 1 Y 2 I 6 = Y 0 Y 1 Y 2 I 7 = Y 0 Y 1 Y 2 I 1 = Y 0 Y 1 Y 2

49. Decoders In this subject, you need to familiarize yourself with two types of decoders:  74LS139 Dual 2-4 Line Decoder.  74LS138 3-8 Line Decoder Decoders are used to:  Activate devices for use by µP.  Memory, I/O interfacing.

50. 74LS139 Dual 2-4 Line Decoder Motorola active low 2-4 decoder. 2 x decoders in one IC. 16 pins total:  2 x (2 inputs, 4 outputs).  Vcc (±5V) and GND.  2 x Enable pins.

51. 74LS139 Dual 2-4 Line Decoder EaEa A 0a A 1a O 0a O 1a O 2a O 3a EbEb A 0b A 1b O 0b O 1b O 2b O 3b

52. 74LS139 Truth Table EI0I0 I1I1 O3O3 O0O0 O1O1 O2O2 1XX1111 0001011 0101101 0011110 0110111

53. 74LS138 3-8 Line Decoder Motorola 3-8 active low decoder. 1 x decoder in one IC. 16 pins total:  3 inputs, 8 outputs (active low).  Vcc (±5V) and GND.  3 x Enable pins.

54. 74LS138 3-8 Line Decoder E1E1 A0A0 A1A1 O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 E2E2 E3E3 A2A2

55. E1E1 I0I0 I1I1 O3O3 O0O0 O1O1 O2O2 1XX1111 XXX1111 XXX1111 0001011 0101101 E2E2 X 1 X 0 0 E3E3 X X 0 1 1 I2I2 X X X 0 0 O7O7 O4O4 O5O5 O6O6 1111 1111 1111 1111 1111 00111100101111 01101110101111 0001111 0101111 0 0 1 1 1 1 1011 1101 00111110111110 01111110110111 74LS138 Truth Table

56. Conclusion

57. Gates: most basic elements in circuits. Gates can be extended to perform advanced functions. Some types are universal (NAND, NOR).

58. Conclusion Flip-flops can store data – feedback:  Can store previous data. Decoders transform code into original signals.  Used in memory interfacing (Chapter 4).

59. Tutorial

60. Name the three basic gates. What are extended gates? What’s the difference between extended gates and basic gates? What is the flip-flop used for?

61. Tutorial Describe the RS, JK, D and Asynchronous flip-flops and draw the truth tables for them. Why are NAND and NOR gates called universal gates? Why are they special?

62. Tutorial Give the definition of decoder. Draw the truth table of the 74LS138 and 74LS139 decoder.

63. The End