2. AB C f Gates are combined into circuits by using the output of one gate as the input for another. So, in these circuits the output depends only on the combination of the inputs.

3. Digital Circuits can also be as memory units. So, in these circuits the output depends on the past state of the inputs and outputs. These type of circuits are called as sequential circuits.

4. Output depends only on inputs. Doesn’t possess any memory elements. There will be no feedback from the output to input. easier to design & faster in operation. Eg: MUX, DEMUX, ADDERS, ENCODERS & DECODERS Output depends on both input and past state outputs. Possess memory elements. Involves some kind of feedback. lots of complexity involves in the design and slower in operation. Eg : Flipflops, latches, registers, counters etc..

5. A Y = ᾹY = Ᾱ AY = Ᾱ 01 10 Ǫ Ǭ 11 0 0 1 At the time of power ON condition, Let us assume the node Q is logic 1

6. Ǫ Ǭ 0 0 1 1 0 QnQn Q n+10 1 0 1 This indicates that the cascade connection of 2 inverters with a feedback is capable of retaining the past information (i.e., capable of storing the past information). And hence it can be considered as a memory element. But, there is no input port and hence we don’t have the control over the data to be stored.

7. ABY0 0 0 1 10 11 1 0 0 0 If A = 0, then Y = B’. This states that if one of the input to NOR gate is grounded, then that NOR gate will act as a NOT gate.

8. Ǫ Ǭ

9. Ǫ Ǭ

10. Ǫ Ǭ But, even with modification, there is no input port and hence we don’t have the control over the data to be stored i.e., we don’t have the control over the output.

11. Ǫ Ǭ R S

12. ABY0 0 0 1 10 11 1 0 0 0 If one of the input is Logic 0, the output will be complement of second input. If one of the input is logic 1, then the output will be logic 0 irrespective of the second input.

13. Ǫ Ǭ R S RSǪǬ10 0 1 0 0 1 01

14. Ǫ Ǭ R S RSǪǬ10 0 0 0 0 1 01 0001 11

15. Ǫ Ǭ R S RSǪǬ10 1 0 01 0001 0110 0 1 0

16. Ǫ Ǭ R S RSǪǬ10 0 0 01 0001 0110 0 1 0 0010 1

17. Ǫ Ǭ R S RSǪǬ10 1 1 01 0001 0110 0 0010 11 Invalid 000 ǪǬ 1 111 00 11 00 00

18. 0 Ǫ Ǭ R S00 ǪǬ 11 00 11 00 00 011 11 00 RSǪǬ1001 0001 0110 0010 11 Invalid00Race Though the input is stable, both 0 and 1 will race with each other at the output.

19. RSǪǬState 1001 0001 0110 0010 11 Invalid00Race SET No Change RESET No Change INVALID RACE

21. Ǫ Ǭ S’ R’ S’R’ǪǬState1001 1101 0110 1110 00 Invalid11Race SET No Change RESET No Change INVALID RACE So, it can be concluded that a 2gate NAND latch can be considered as an ACTIVE LOW latch.

22. S’R’ǪǬState 1001 1101 0110 1110 00 Invalid11Race SET No ChangeNo Change RESET INVALID RACE

23. S’ R’ CSRS’R’ǪǬState11-- 11-- 0110 1001 No ChangeNo Change RESET SET X0X 010 011 110 0011 Invalid 111

24. CQnQn SR Ǫ n+1 Statexx0 000 100 100 No Change RESET 00 10 10 11 No Change 11x Invalid 10 xx1 01 No Change 001 No Change 11 RESET 011 011 SET 10 11 SET Invalid 11x 11

25. QnQn SR 000 100 100 0 0 1 11x 0 001 1 011 011 0 1 11x 1 0132 4576 Characteristic Equation

26. 0 0 1 1 0 0, 0 1 0 0, 1 0 1 0 0 1

27. Latch is a memory element which is capable of storing one bit (either 0 or 1). A Latch contains two output lines which are always complement to ach other. A NOR latch is an ACTIVE HIGH latch. A NAND latch is an ACTIVE LOW latch. In order to enable or disable any latch to accept the input data, control signal line can be used to convert latches into controlled latches. A controlled NAND latch is active high latch. Generally, invalid state or RACE condition occurs in latches for certain pattern of inputs which are undesired and must be eliminated.

29. CDSRǪǬStateXX-- 1010 0101 Reset Set X0 0 1 1 1 No ChangeNo Change Characteristic Equation

30. Why are the input terminals named as J,K??

31. CJKS’R’ǪǬState11-- 11-- 10 No ChangeNo Change RESET X0X 010 011 1 1 0 1 1 ?01 0 1 1(0)(1) 10 1 0 0(0)(1)

32. CJKS’R’ǪǬState11-- 11-- 10 01 No ChangeNo Change RESET SET X0X 010 011 110 1 1 0 1 ?01 0 1 0(1)(0) 10 1 0 1(1)(0)

33. CJKS’R’ǪǬState11-- 11-- 10 01 No ChangeNo Change RESET SET X0X 010 011 110 Toggle 111 1 1 ?01 0 1 0(1)(0) 10 1 0 1(0)(1) ?10

34. CQnQn JK Ǫ n+1 Statexx0 000 100 100 No Change RESET 00 10 10 11 No Change 111 Toggle 10 xx1 01 No Change 001 No Change 11 RESET 011 011 SET 10 11 SET Toggle 110 11

35. QnQn JK 000 100 100 0 0 1 111 0 001 1 011 011 0 1 110 1 0132 4576 Characteristic Equation

36. 0 0 1 1 0 0, 0 1 0 0, 1 0 1 0, 1 1 0 1, 1 1

38. CTJKǪǬStateXX-- 00-- 11-- No ChangeNo Change Toggle X0 0 1 1 1 Characteristic Equation

39. If the response time (time required for the output to respond for a corresponding change in input) of any latch is assumed be 1nS. Then, it can be concluded that, for a T latch, the output toggles for 10 times if toggle state input (T=1) is in high state for 10nS. For RS latch, RACE condition occurs for 10 times if the corresponding inputs (R=S=1) are high for 10nS. These rapid changes in the output are undesirable and must be avoided.

40. So, these hazards can be eliminated by enabling the latch only once in a complete cycle.

41. Master – Slave Configuration of JK Latches

42. In a complete Cycle (which is spread over a period of 20nS, The flip-flop responds only once i.e., only during the falling edge. This makes it possible to eliminate the race around condition in latches.

43. So, these hazards can be eliminated by enabling the latch only once in a complete cycle. So, it would be better to make the memory elements edge sensitive instead of level sensitive. Because, edges will occur only once in a cycle. Edge sensitive memory elements are called flip-flops. Latches are level sensitive and flip-flops are edge sensitive. Latches will respond many no. of times in a single clk cycle. But, flipflops will respond only once in a cycle.