1. LNL 1 SADIRC2000 Resoconto 2000 e Richieste LNL per il 2001 L. Berti 30% M. Biasotto 100% M. Gulmini 50% G. Maron 50% N. Toniolo 30% Le percentuali sono condivise con INFN-GRID

2. LNL 2 40 MHz 10 5 Hz 10 2 Hz 100 Tbyte/s 100 Gbyte/s 100 Mbyte/s Level 1 Trigger Event Manager Detector Frontend Event Builder Computing Services Controls Readout Filter Collision rate40 MHz Level-1 Maximum trigger rate100 kHz Average event size1 Mbyte No. of In-Out units (200-5000 byte/event)1000 Event builder (512-512 switch) bandwidth500 Gbit/s Event filter computing power5 10 6 MIPS Data productionTbyte/day No. of readout crates250 No. of electronic boards10000 Collision rate40 MHz Level-1 Maximum trigger rate100 kHz Average event size1 Mbyte No. of In-Out units (200-5000 byte/event)1000 Event builder (512-512 switch) bandwidth500 Gbit/s Event filter computing power5 10 6 MIPS Data productionTbyte/day No. of readout crates250 No. of electronic boards10000 Units Future DAQ Systems

3. LNL 3 Sadirc2000 Event Builder Demonstrators Square Event Builder (15x15): June 2000 (OK)Square Event Builder (15x15): June 2000 (OK) Asymmetric Event Builder (4x40):November 2000Asymmetric Event Builder (4x40):November 2000

4. LNL 4 Hardware components for the Square EB SysKonnect SK-9821 1000BaseT adapter Foundrynet FastIron II+ 1000BaseT switch Supermicro PIIIDME motherboard Intel 840 chipset Pentium III 600 Mhz 64/66 PCI BUS

5. LNL 5 Software components for the Square EB vxWorks real time o/s C++ software for emulation of the Event Builder components ( EVM, RU, BU ) Standard vxWorks driver for the SysKonnect adapter

6. LNL 6 Error recovery Error recovery procedure implemented See: Samim Erhan, Wolfgang Schleifer, Nick Sinanis ‘System Error Analysis’ TriDAS Review 11 May 2000

7. LNL 7 Error recovery BU send RU send timer start cache send ( retry ) start cancel timeout cache BU allocate EVM allocate timer start confirm allocate start cancel timeout confirm BU – EVM communication BU – RU communication

8. LNL 8 Square Event builder layout RUs and BUs distributed in all the switch slots Part of the traffic localized in the slot Minimize the switch backplane utilization 1 1514 1312 1110 9 8 7 6 543 2 1 1514 1312 1110 9 8 7 6 543 2 EVM RUs BUs Slot 1 Slot 2 Slot 3 Slot 4

9. LNL 9 Switch packets loss in special condition First packet forwarded correctly Some packets lost ( 10-30 packets ) All the following packets forwarded correctly The switch lose some packets in particular conditions When the transmission restart after a pause >60 Secs Probably related to the MAC address table management Problem solved by the Error recovery procedure

10. LNL 10 Test conditions BDN+BCN in the same network No Readout commands from EVM to RU Clear/Allocate optimization: the clear command is sent together an allocate for a new event No command or event aggregation: each packet transport a command or a data frame relative to a single event

11. LNL 11 Test conditions Full data transfer: data moved from/to the pc memory Tests performed in the 400-4000 Bytes range

12. LNL 12 Throughput vs number of allocated events 15 x 15

13. LNL 13 Throughput vs event size

14. LNL 14 Event rate vs event size

15. LNL 15 BU balancing 15 x 15

16. LNL 16 Event builder scaling

17. LNL 17 Aggregate throughput

18. LNL 18 Conclusions for the Square Event Builder Event Builder Demonstrator 15x15 based on copper Gigabit Ethernet interfaces tested Good performances and scalability Actual limit is in the Readout Unit (?) Error recovery work fine, systematic tests need

19. LNL 19 Next Steps for 2000 Asymmetric Event Builder (4x40) Event Builder Protocol Simulations

20. LNL 20 Next Steps for 2001: InfiniBand (I) TODAY

21. LNL 21 InfiniBand (II) Legacy host architecture The Infiniband Model

22. LNL 22 InfiniBand (III) What?What? –Initial single link signaling rate of 2.5Gbaud Means unidirectional transfer rate of 250MB/sec with a theoretical full duplex rate of 500MB/secMeans unidirectional transfer rate of 250MB/sec with a theoretical full duplex rate of 500MB/sec –Initial support for single, 4, and 12 wide link widths –Point to point switched fabric –Message based with multicasting support MultiStageSwitch Links TCA I/O Controller Memory Controller PCI-X Host Bridges CPUCPU CPUCPU HCA Link Fibre Channel SCSI Gig. Ethernet Memory HCA- Host Channel Adapter TCA - Target Channel Adapter

23. LNL 23 SADIRC Requests for 2001 SADIRC Requests for 2001 Simple test system (4 servers + Storage Area Network + Network) for 2001 is possibleSimple test system (4 servers + Storage Area Network + Network) for 2001 is possible Early access to the productsEarly access to the products Test BedsTest Beds Requests 2001 (valuations)Requests 2001 (valuations) 4 servers50 Ml 4 servers50 Ml 1 IBA Switch20 Ml 1 IBA Switch20 Ml IBA Adapters10 Ml IBA Adapters10 Ml

24. LNL 24 SADIRC2000 Global Requests SADIRC2000 Global Requests