1. Final Presentation Winter 2010 Performed by: Tomer Michaeli 052792769 Liav Cohen 301242509 Supervisor: Shlomo Beer Gingold In collaboration with: characterization of synchronizers and metastability and metastability

2. Project subject Direct measurements of synchronization Circuits and comparison to results on chip [5].

3. Project goals Learn the direct measurement method. Building and improving of a measurement system for synchronization to characterize performance of synchronizers. Comparison to measurements results on chip [5]

4. Achievements Learning the measurement system. Learning the chip characteristics and its GUI. Learning a technique to get and save scope’s measurements. Measuring synchronizer metastability Analyzing the results Comparing to results on chip.

5. Theoretical background Many Globally Asynchronous Locally Synchronous (GALS) systems are susceptible to failure because of a Tsetup / Thold violation. In order to prevent that we use synchronizers A common way of implementation is with N cascaded FF’s which have the target system’s clock

6. Theoretical background - cont. A schematic figure of the system:

7. Theoretical background - cont. The main index which defines the system reliability is Mean Time Between Failures (MTBF): While –  Fc and Fd are the receiver and sender system frequencies, respectively.  is a parameter related to the synchronizer input.  is the resolution time constant  S is the predetermined time for metastbility resolution and defined as N is the number of cascaded FF’s and.

8. Theoretical background - cont.

9. As technology improves, the frequency scaling reduces the MTBF The parameter in equation (1) is predominant since its effect on MTBF is exponential. To maintain high MTBF, the factor has to lessen, and that was the common assumption.

10. Theoretical background - cont. An article, which was published recently, contradicts this assumption [2] In the project we will examine those results

11. Project environment Signal generator Test Chip 65nm FPGA board DLP socket (PC)MUX socket DSO80204B Agilent oscilloscope

12. Project Environment-cont. The test environment is composed by the FPGA board that generates control And data signals for the 65nm Synchronizer test chip. The FPGA board is controlled through USB (from PC) using a special DLP Socket and a dedicated software. DLP chip USB cable (from PC) Control and data Signals to/from TC

13. Top level design Fd [Hz] Fc [Hz] synchronizer DSO80204B Scope Input TRIGGER Data PC Ch1-Ch2

14. Searching for metastability Fd (data) 1/Fd [ns] Fc (clock) 1/Fc [ns] Synchronizer output The frequency of the synchronizer output is (Fc-Fd) [Hz] Considerations in choosing the frequencies:  The frequencies Fc,Fd should be high.  Choosing the difference (Fc-Fd) to be low, increases the chance for metastablity,but decreases the cases to measure. (Fc-Fd) [Hz]

15. Measurements Measurements were performed at Vdd=1.1V and room temperature  2 DATA frequencies 3.125 [MHz] and 6.245 [MHz] were measured and clock frequency 6.25 [MHz]  Measurement period time: T=200 [sec] for each delay value.  Measurements were executed on 3 different chips  Results analyzing by MATLAB

16. Measurements- JITTER Calculating the measurements noise for a square signal with frequency=6.25 [MHz]: Noise measurement ~ 50 [psec] noise

17. Top level design Fd [Hz] Fc [Hz] synchronizer clock (Input) Data (TRIGGER) PC 3.125MHz \ 6.245MHz 6.25MHz Choosing one of the synchronization circuits : -regular FF -synchronizer 1 -synchronizer 2 F_data=(Fc-Fd)[Hz] Calculating the delay between clock rising to data rising by the scope Getting the measurements values from scope to PC by VEE program

18. synchronization circuits Choosing one of the synchronization circuits : Regular FF Synchronizer 1 Synchronizer 2

19. Measurements  Calculating,by the scope, the delay between the DATA signal (synchronizer output) and the clock signal (Ch1-Ch2), which mean the delay between clock rising to the data stabilizing

20. Measurements  Getting the measurements values from the scope to PC by VEE program (with GPIB connection):

21. Measurements  Creating histogram for N samples. 1M samples histogram

22. Measurements  Calculate number of measurements up to delay S [sec] (‘reversed distribution function’).

23. Measurments Using the equation: after some math: Drawing the graph for equation (3) which its slope is and finding. Calculating :

24. Measurements Graphs for a regular FF with Frequencies Fc=6.25 MHz and Fd=3.125 MHz and its parameter Varying slope-calculating para’ for 2 segments. Slope= LD (long delay) SD (short delay) SD LD

25. Results Similar graphs were made for synchronizer 1 circuit and for synchronizer 2 circuit [5] on 3 different chips. The synchronization parameters and were calculated from the graphs.

26. Results – cont. [psec]

27. Results-cont. results on/off chip: Previous results [psec]

28. Conclusions The test result for is in the same order of magnitude as the on chip results The structure of the synchronizer effects much on the value of. As opposed to the previous measurements, we get the highest value of for regular FF circuit and the lowest value for synchronizer 2 circuit (XOR feedback FF).

29. Conclusions A measurement noise distorted some of the results additional tests on chips should be made in order to get more statistics

30. References 1.Yaron Semiat and Ran Ginosar, ‘Timing Measurements of Synchronization Circuits’, Technion, Haifa, 2003. 2.Shlomo Beer Gingold, ‘Test Chip (Sinc_test_chip)’, Technion, Haifa. 3.Salomon beer,Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and Avinoam Kolodny, 'The Devolution of synchronizers', Technion, Haifa, 2010. 4. Lindsay Kleeman & Antonio Cantoni, 'Metastable Behavior in Digital Systems', University of Newcastle, New South Wales, 1987. 5.Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and Avinoam Kolodny, 'An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm', Technion, Haifa. 6.DLP Design, 'DLP-USB245M-G USB to FIFO Parallel Inetrface Module', 1605 Roma Lane, Allen TX 75013. 7. 'Xilinx University Program Virtex-ll Pro Development System', UG069, March 8,2005