1. Kazi ECE 6811 ECE 681 VLSI Design Automation Khurram Kazi Thanks to Automation press THE button outcomes the Chip !!! Reality or Myth

2. Kazi ECE 681 2 Introduction to Verilog Present day ASIC/FPGA designers most likely have to work with VHDL and Verilog in one form or another. People who used VHDL mostly, are likely to encounter Verilog as the language that describes the gate level netlist. Good to know both HDLs. Both have their strong points and have weaknesses.

3. Kazi ECE 681 3 Verilog Vs VHDL Verilog is perceived to be loosely typed language. VHDL strongly typed language. Fact of the matter is that ones choice of VHDL over Verilog or vice versa most likely tends to be based ones familiarity with either of the languages or company’s past history of development platform. Both languages serve as an excellent tool for RTL development. Neither of them is well suited for the verification of complex ASICs especially that are algorithmic intensive. Languages like specman ‘e’, Synopsys “vera” or C/C++ have become the languages of choice for verification platform.

4. Kazi ECE 681 4 Our game plan for the next few weeks Over the next few weeks I will be giving you an overview of Verilog with synthesis in mind. Verilog as the language for netlist representation. Start using specman “e” for the test benches. Keep discussing other networking protocols and functions while working through the languages. Any synthesis and gate level simulation issues that come up will be discussed as the tools are up and running.

5. Kazi ECE 681 5 Syntax used in describing a module Module is a fundamental block in Verilog that is synonymous to entity. Verilog does not support different architectures for the same entity module (port list); endmodule

6. Kazi ECE 681 6 Continuous assignment This is synonymous to concurrent block statement in VHDL // get continuously updated whenever any of the input operands // change value. module new_or ( a b c ); input a; input b; output c; assign c = (a | b); // using & would have performed and function endmodule

7. Kazi ECE 681 7 Initial block // Initial block consists of a statement or a group of statements enclosed in a begin and // end which will be executed only once at simulation time 0. If there is more than one // initial block they get executed concurrently independent of each other. Normally used // for initializing, monitoring, generating clocks etc. module stimulus1 initial reset_n = 1’b0; #25 reset_n = 1’b1; initial begin // multiple statements have to be lumped together variable1 = 0; #10 variable1 = 1; #10 variable1 = 0 #30 variable1 = 1; #50 variable1 = 0; end;

8. Kazi ECE 681 8 Always block // statements in the “always” block repeatedly get executed until the simulation is // stopped by $finish or $stop. Similar to a process in VHDL // Block that generates a clock module clk_gen reg clk; Intial begin clk = 1’b0; // setting the initial value of the clock end always begin #25 clk = ~clk; // clock repeating every 50 time units end Intial begin #5000 $finish; // simulation ends after 5000 time units end endmodule clk_gen

9. Kazi ECE 681 9 Module instantiation (by position) module couple_of_ands ( a, b, c, d ); input a; input b; input c; output d wire w1; // two instances of the module testands testands and1 (a, b, w1); // assuming the 1 st two ports are inputs and 3 rd // is the output of the and gate testands and2 (w1, c, d); endmodule

10. Kazi ECE 681 10 Module instantiation (connectivity by name) module mux4cbn ( out, a, b, sel ); output [3:0] out; input [3:0] a, b; input sel; // the inputs and output of the mux2 are 2 bits wide Mux2hi (.a(a[3:2]),.b(b[3:2]),.sel(sel),.out(out3:2]) ); Mux2lo (.a(a[1:0]),.b(b[1:0]),.out([out3:2]),.sel(sel) ); endmodule Name of net being connected.portname(net_to_be_connected) Name of port in lower level module (period indicating a hierarchical name)

11. Kazi ECE 681 11 Data Objects Nets –Nets sometimes called to wires are most common data objects to interconnect modules. The default net type is a plain wire. There are wired OR, wired AND, pullups, pulldowns etc. For synthesis use wire only!! wire a, b, c; // three 1-bit nets of type wire wire [7:0] d, e, f; // three 8-bit vectors Verilog implicitly declares nets for every port declaration. Every connection made in a module instance or primitive instance is also implicitly declared as a net, if it isn’t already declared.

12. Kazi ECE 681 12 Registers The register (reg) data object holds its value from one procedural assignment statement to the next and holds its value from one to the next simulation cycle. It DOES NOT imply that a physical register will be synthesized.The fundamental difference between nets and registers is that the registers have to be assigned values explicitly. Once a value is assigned to a register, it is held until next procedural assignment to it.

13. Kazi ECE 681 13 Registers and Ports Only output port can be of type reg, since only way to get a value into a reg is with a procedural statement. Input ports cannot be of type reg since they do not get their value through procedural assignment. Relationship between ports and reg is shown below: Inputs: Reg or net outside net only inside net or reg inside outputs: Net only outside inout: net only inside inout: net only outide

14. Kazi ECE 681 14 Numbers Number of bits ‘ radixValue ‘b ‘B Binary ‘d ‘D Decimal ‘h ‘H Hexadecimal ‘o ‘O Octal 8’b10010001 8’d245

15. Kazi ECE 681 15 Description of a flip flop module fflop (q, data, reset_n, clk); output q; input data, reset_n, clk; reg q; always @(posedge clk) if (reset_n == 0) // this can also be written as “if (!reset_n)” q = 1’b0; else q = data; endmodule // fflop

16. Kazi ECE 681 16 Description of a flip flop with asynchronous reset_n module fflop_async (q, data, reset_n, clk); output q; input data, reset_n, clk; reg q; always @(posedge clk or negedge reset_n) if (!reset_n) q = 1’b0; else q = data; endmodule // fflop_async ** Since the clk is not used in any conditional statement, hence implicitly the synthesis tool knows that clk is the CLOCK signal

17. Kazi ECE 681 17 Arithmetic operators Binary: +, -, *, /, % (the modulus operator) Unary: +, - Integer division truncates any fractional part The result of a modulus operation takes the sign of the first operand If any operand bit value is the unknown value x, then the entire result value is x Register data types are used as unsigned values –negative numbers are stored in two’s complement form

18. Kazi ECE 681 18 Relational Operators a<b a less than b a>b a greater than b a<=b a less than or equal to b a>=b a greater than or equal to b –The result is a scalar value: –0 if the relation is false –1 if the relation is true –x results if any of the operands has unknown x bits –Note: If a value is x or z, then the result of that test is false

19. Kazi ECE 681 19 Equality Operators a === ba equal to b, including x and z a !== ba not equal to b, including x and z a == ba equal to b, resulting may be unknown a != ba not equal to b, result may be unknown –Operands are compared bit by bit, with zero filling if the two operands do not have the same length –Result is 0 (false) or 1 (true) –For the == and != operators the result is x, if either operand contains an x or a z –For the === and !== operators bits with x and z are included in the comparison and must match for the result to be true the result is always 0 or 1

20. Kazi ECE 681 20 Logical Operators ! logic negation && logical and || logical or Expressions connected by && and || are evaluated from left to right Evaluation stops as soon as the result is known The result is a scalar value: –0 if the relation is false –1 if the relation is true –x if any of the operands has unknown x bits

21. Kazi ECE 681 21 Bit-wise operators ~ negation & and | inclusive or ^ exclusive or ^~ or ~^ exclusive nor (equivalence) Computations include unknown bits, in the following way: – ~x = x –0&x = 0 –1&x = x&x = x –1|x = 1 – 0|x = x|x = x –0^x = 1^x = x^x = x – 0^~x = 1^~x = x^~x = x When operands are of unequal bit length, the shorter operand is zero-filled in the most significant bit positions

22. Kazi ECE 681 22 Combinatorial and Sequential logic partitioning

23. Kazi ECE 681 23 if else if else syntax

24. Kazi ECE 681 24 case statement

25. Kazi ECE 681 25 for loop synthesis integer i; always @ (a or b) begin for (i = 0; i < 6; i = i + 1) example[i] = a[i] & b [5 – i]; end Example(0) <= a(0) and b(5); Example(1) <= a(1) and b(4); Example(2) <= a(2) and b(3); Example(3) <= a(3) and b(2); Example(4) <= a(4) and b(1); Example(5) <= a(5) and b(0); for loops are “unrolled” and then synthesized.

26. Kazi ECE 681 26 Basic Verilog file // Use two slashes for comments module simple_counter ( reset_n, sys_clk, enable, count8 ); //end port list // Input ports declaration input reset_n; input sys_clk; input enable; // Output ports output [3:0] count8; // Input ports Data Type // By rule all the input ports should be wires wire clock; //by default they are and don’t wire reset; // need to specify as wire wire enable; // Output ports data type // Output ports can be storage elements or a wire reg [3:0] count8; //Code start // Counter uses +ve edge triggered and // has synchronous reset_n always @ (posedge clock) begin : COUNT // Block Name if (reset_n == 1'b1) begin counter_out <= 4'b000; end // Counter counts when enable is 1 else if (enable == 1'b1) begin counter_out <= counter_out + 1; end end // end of block COUNT endmodule // end of module // simple_counter

27. Kazi ECE 681 27 Basic FIFO Write pointer Data in Read pointer Data out FIFO full FIFO empty FIFO almost full FIFO almost empty FIFO used for rate adaptation Buffering temporarily Normally has two different clocks Can be RAM based or Flip flop based

28. Kazi ECE 681 28 Reading Assignment http://www.csix.org/csixl1.pdf Please read it and see if it makes sense to you. We will discuss it in the upcoming lecture.