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Cyclic Combinational Circuits and Other Novel Constructs Marrella splendensCyclic circuit (500 million year old Trilobite)(novel construct)
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inputsoutputs The current outputs depend only on the current inputs. Combinational Circuits combinational logic
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NAND OR AND NOR 1 0 0 1 1 1 1 0 1 0 0 1 Acyclic (i.e., feed-forward) circuits are always combinational. Combinational Circuits
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Synthesis General methodology: optimize by introducing feedback in the substitution/minimization phase. Developed a tool called CYCLIFY within Berkeley SIS Environment. Optimizations are significant and applicable to a wide range of circuits. Design a circuit to meet a specification.
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Example: 7 Segment Display Inputs a b c d e f g Output 1001 0001 1110 0110 1010 0010 1100 0100 1000 0000 0123 xxxx 9 8 7 6 5 4 3 2 1 0
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Example: 7 Segment Display a b c d e f g Output
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Substitution Basic minimization/restructuring operation: express a function in terms of other functions. Substitute b into a: (cost 9) a ))(( 302321320 xxxxxxxxx (cost 8) Substitute c into a: (cost 5) Substitute c, d into a: (cost 4) a )( 323212 bxxxxxbx a cxxcx 321 a dccx 1
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Substitution/Minimization Berkeley SIS Tool a ))(( 302321320 xxxxxxxxx },,,{fdcb target function substitutional set a dccx 1 low-cost expression
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Acyclic Substitution g f e b a c d Select an acyclic topological ordering: g f e d c b a
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g f d c b a edcaxx 21 dccx 1 xxxxxxxxx 102213321 ))((dxxxxxx 102320 )(cdxx 10 )( Select an acyclic topological ordering: Area (literal count): 37 Acyclic Substitution e 3 cxb d ba f
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Select an acyclic topological ordering: Nodes at the top benefit little from substitution. g f d c b a edcaxx 21 dccx 1 xxxxxxxxx 102213321 ))((dxxxxxx 102320 )(cdxx 10 )( e 3 cxb d ba f
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Cyclic Substitution How can we find a cyclic solution that is combinational? g f d c b a e ?
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Target Candidates Simpler Example: Cyclic Substitution
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Target Candidates Simpler Example: Cyclic Substitution
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Target Candidates Simpler Example: Cyclic Substitution
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“Break-Down” approach Search performed outside space of combinational solutions. Terminates on optimal solution * cost 12 cost 13 cost 12 cost 13 combinational cost 14 Branch and Bound
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“Build-Up” approach cost 17 cost 16 cost 15 not combinational cost 14 Branch ( without Bounding ) cost 13 best solution Search performed inside space of combinational solutions
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g f e d c b a Area (literal count): 34 Combinational solution: xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Example: 7 Segment Display
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Limit the density of edges a priori Limit breadth Tunnel depth-wise (with backtracking) Branch and Bound Heuristics: for target functions, configurations n Large search space: (See “The Synthesis of Cyclic Circuits,” DAC, ’03)
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Optimization for Area Number of NAND2/NOR2 gates for Berkeley SIS vs. CYCLIFYsolutions BenchmarkBerkeley SISCYCLIFYImprovement 5xp120318210.34% ex619415221.65% planet9438895.73% s3862312223.90% bw30225515.56% cse3443294.36% pma4093933.91% s5105144836.03% duke284767320.54% styr85875811.66% s1488108410037.47% Based on “script.rugged” sequence and technology mapping.
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Optimization for Area and Delay Berkeley SISCYCLIFY benchmarkAreaDelayAreaImprovementDelayImprovement p82175191674.57%1521.05% t1343173274.66%1417.65% in3599405931.00%3317.50% in2590345585.42%2914.71% 5xp12102318014.29%224.35% bw280282549.29%2028.57% s510452284441.77%2414.29% s1566365424.24%3113.89% duke2742387163.50%3410.53% s14881016439952.07%3420.93% s149410904610791.01%3915.22% Number of NAND2/NOR2 gates and the Delay of Berkeley SIS vs. CYCLIFY solutions Based on “script.delay” sequence and technology mapping.
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Practice Improvements in area (and consequently power) and delay are significant. Similar improvements were obtained for larger scale circuits: e.g., the ALU of an 8051 microprocessor. E.D.A. companies (Altera and Synopsys) have expressed strong interest.
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Synthesis General methodology: optimize by introducing feedback in the substitution/minimization phase. Optimizations are significant and applicable to a wide range of circuits. Design a circuit to meet a specification.
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Example: 7 Segment Display Inputs a b c d e f g Output 1001 0001 1110 0110 1010 0010 1100 0100 1000 0000 0123 xxxx 9 8 7 6 5 4 3 2 1 0
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Example: 7 Segment Display a b c d e f g Output
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Substitution/Minimization Basic minimization/restructuring operation: express a function in terms of other functions. Substitute b into a: (cost 9) a ))(( 302321320 xxxxxxxxx (cost 8) Substitute c into a: (cost 5) Substitute c, d into a: (cost 4) a )( 323212 bxxxxxbx a cxxcx 321 a dccx 1
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Substitution/Minimization Berkeley SIS Tool a ))(( 302321320 xxxxxxxxx },,,{fdcb target function substitutional set a dccx 1 low-cost expression
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Acyclic Substitution g f e b a c d Select an acyclic topological ordering: g f e d c b a
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g f d c b a edcaxx 21 dccx 1 xxxxxxxxx 102213321 ))((dxxxxxx 102320 )(cdxx 10 )( Select an acyclic topological ordering: Cost (literal count): 37 Acyclic Substitution e 3 cxb d ba f
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Select an acyclic topological ordering: Nodes at the top benefit little from substitution. g f d c b a edcaxx 21 dccx 1 xxxxxxxxx 102213321 ))((dxxxxxx 102320 )(cdxx 10 )( e 3 cxb d ba f
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Cyclic Substitution Try substituting every other function into each function: Not combinational! Cost (literal count): 30 0 1 ex dccx fba geex bcdx gxaxex egxxax 2 3 321 202 f g f d c b a e
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Cost 30 Lower bound Cost 37 Upper bound Acyclic substitution Unordered substitution Cyclic solution? Cost 34
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Cyclic Substitution g f e d c b a Cost (literal count): 34 Combinational solution: xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f
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Cyclic Substitution Cost (literal count): 34 Combinational solution: topological cycles g f e d c b a xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f
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Inputs x 3, x 2, x 1, x 0 Cost (literal count): 34 ba ga e e e c 1 no electrical cycles Cyclic Substitution g f e d c b a xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f = [0,0,1,0]:
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g f e d c b a Cost (literal count): 34 ba ga e e e c 1 1 1 0 1 1 1 0 Cyclic Substitution no electrical cycles xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:
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g f e d c b a Cost (literal count): 34 ba ga e e e c 1 1 1 0 1 1 1 0 a b c d e f g Cyclic Substitution xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:
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g f e d c b a Cost (literal count): 34 ba ga e e e c 1 1 1 0 1 1 1 0 a b c d e f g Cyclic Substitution xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:
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g f e d c b a Cost (literal count): 34 ba ga e e e c 1 1 1 0 1 1 1 0 a b c d e f g Cyclic Substitution xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:
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g f e d c b a Cost (literal count): 34 Cyclic Substitution xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:
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g f e d c b a Cost (literal count): 34 Cyclic Substitution ba a a 1 0 c f xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]: no electrical cycles
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g f e d c b a Cost (literal count): 34 1 0 1 0 1 1 1 Cyclic Substitution ba a a 1 0 c f xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f no electrical cycles Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:
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g f e d c b a Cost (literal count): 34 a b c d e f g Cyclic Substitution 1 0 1 0 1 1 1 ba a a 1 0 c f xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:
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g f e d c b a Cost (literal count): 34 Cyclic Substitution 1 0 1 0 1 1 1 ba a a 1 0 c f a b d e f g xe 0 bxa 3 gxxxax 1023 )( axxex 321 )( exxxxxx 312320 )( cxxcx 301 xxxfx 1023 )( f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]: c
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Synthesis Strategy: Allow cycles in the substitution phase of logic synthesis. Find lowest-cost combinational solution. 21213 321321 312321 )( )( )( xxxxxc xxxxxxb xxxxxxa Collapsed: Cost: 17 321 1321 323 xxaxc cxxxxb xxbxa Solution: Cost: 13
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“Break-Down” approach Exclude edges Search performed outside space of combinational solutions cost 12 cost 13 cost 12 cost 13 combinational cost 14 Branch and Bound
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“Build-Up” approach Include edges Search performed inside space of combinational solutions cost 17 cost 16 cost 15 not combinational cost 14 Branch and Bound cost 13 best solution
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Implementation: CYCLIFY Program Incorporated synthesis methodology in a general logic synthesis environment (Berkeley SIS package). Trials on wide range of circuits –randomly generated –benchmarks –industrial designs. Consistently successful at finding superior cyclic solutions.
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Benchmark Circuits Cost (literals in factored form) of Berkeley SIS Simplify vs. Cyclify Circuit# Inputs# OutputsBerkeleySimplifyCaltechCyclifyImprovement dc147393412.80% ex6811857610.60% p825141049013.50% t41281098918.30% bbsse11 11810610.20% sse11 11810610.20% 5xp171012310911.40% s38611 13111313.70% dk17101116013615.00% apla101218513129.20% tms81618515814.60% cse11 21217716.50% clip9521318911.30% m281623120710.40% s510251326022712.70% t1212327320624.50% ex1132430927610.70% exp81832026218.10%
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Benchmarks Example: EXP circuit Cyclic Solution (Caltech CYCLIFY ): cost 262 Acyclic Solution (Berkeley SIS ): cost 320 cost measured by the literal count in the substitute/minimize phase
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Discussion A new definition for the term “combinational circuit”: a directed, possibly cyclic, collection of logic gates. Most circuits can be optimized with feedback. Optimizations are significant. Paradigm shift:
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