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BJT Emitter Stabilized Bias

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Presentation on theme: "BJT Emitter Stabilized Bias"— Presentation transcript:

1 BJT Emitter Stabilized Bias
ELEC 121

2 Improved Bias Stability
The addition of RE to the Emitter circuit improves the stability of a transistor output Stability refers to a bias circuit in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor forward current gain () The temperature (TA or ambient temperature) surrounding the transistor circuit is not always constant Therefore, the transistor  is not a constant value January 2004 ELEC 121

3 BJT Emitter Bias Draw Equivalent Input circuit
Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point Graphical Solution using Loadlines Perform a Computational Analysis January 2004 ELEC 121

4 Emitter-Stabilized Bias Circuit
Adding an emitter resistor to the circuit between the emitter lead and ground stabilizes the bias circuit over Fixed Bias January 2004 ELEC 121

5 Base-Emitter Loop January 2004 ELEC 121

6 Equivalent Network January 2004 ELEC 121

7 Reflected Input impedance of RE
January 2004 ELEC 121

8 Base-Emitter Loop Applying Kirchoffs voltage law: - VCC + IB RB + VBE +IE RE = 0 Since: IE = ( + 1) IB We can write: VCC + IB RB + VBE + ( + 1) IB RE = 0 Grouping terms and solving for IB: Or we could solve for IE with: January 2004 ELEC 121

9 Collector-Emitter Loop
January 2004 ELEC 121

10 Collector-Emitter Loop
Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0 Assuming that IE  IC and solving for VCE: VCE = VCC – IC (RC + RE) If we can not use IE  IC the IC = IE and: VCE = VCC – IC (RC + RE) Solve for VE: VE = IE RE Solve for VC: VC = VCC - IC RC or VC = VCE + IE RE Solve for VB: VB = VCC - IB RB VB = VBE + IE RE January 2004 ELEC 121

11 Transistor Saturation
At saturation, VCE is at a minimum We will find the value VCEsat = 0.2V For load line analysis, we use VCE = 0 To solve for ICSAT, use the output KVL equation: January 2004 ELEC 121

12 Load Line Analysis The load line end points can be calculated:
At cutoff: At saturation: January 2004 ELEC 121

13 Emitter Stabilized Bias Circuit Example
January 2004 ELEC 121

14 Design of an Emitter Bias CE Amplifier
ELEC 121 January 2004 Design of an Emitter Bias CE Amplifier Where .1VCC  VE  .2VCC And VCC  VC  .6VCC January 2004 ELEC 121 Fixed Bias

15 Emitter Bias with Dual Supply
January 2004 ELEC 121

16 Emitter Bias with Dual Supply
Input Output January 2004 ELEC 121


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