1. Pixel Sensors for a Linear Collider from Physics Requirements to Beam Test Validation M Battaglia UC Berkeley and LBNL with P Denes, D Bisello, D Contarato, P Giubilato, L Glesener, B Hooberman, C Vu KEK, January 30, 2008

2. Requirements for ILC Vertexing a (  m)b (  m GeV) LEP2570 SLD 833 LHC1270 RHIC II 1412 ILC 510 ILC Vertexing Mokka+MarlinReco

3. Towards multi-TeV

4. Requirements for the Vertex Tracker Asymptotic I.P. Resolution [ a ] Multiple Scattering I.P. Term [ b ] Polar Angle Coverage Space / Time Granularity Technology (pitch, S/N) Geometry (R in, R out ) Technology (thickness) Geometry (R in, N Layers ) Technology (r/o electronics) Geometry (z Layers ) Technology (pitch, r/o architecture, r/o time) Geometry (R in )

5. Effect of VTX performance on accuracy of BR(H 0  bb, cc, gg) at 0.35-0.5 TeV already assessed by various studies using parametric simulation: Yu et al. J. Korean Phys. Soc. 50 (2007); Kuhl, Desch LC-PHSM-2007-001; Ciborowski,Luzniak Snowmass 2005 ChannelChangeRel. Change in Stat. Uncertainty H  bb H  cc H  gg Geometry: 5  4 layer VTX Thickness: 50  m  100  m + 0% +15% + 5% H  cc  point : 4  m  6  m 4  m  2  m +10% -10% H  cc Thickness: 50  m  100  m +10% Physics vs. VTX configuration Higgs BRs accuracy vs. I.P. Resolution

6. Geometry  IP (  m) R in 1.2 cm  1.7 cm c purity=0.7  c = 0.49  c = 0.46 R in 1.2 cm  2.1 cm c purity=0.7  c = 0.49  c = 0.40 HPS c purity=0.7  c = 0.29 Hawking, LC-PHSM-2000-021 Physics vs. VTX configuration Charm Tagging vs. I.P. Resolution Study change in efficiency of charm tagging in Z 0 -like flavour composition

7. Parametrising the Vertex Tracker Response Provide extrap. resolution for various set of parameters (R in, ladder thickness,...) and VXD models obtained using G4 + Kalman Filter Fit:  extrap vs. p and  for isolated trks and ptcs in jets. Example:  extrap vs. p for isolated  s baseline VXD02, ladder thickness x 2, R in = 18 mm :

8. Pair Background and VTX Detector Geometry of innermost layer bound by distribution of incoherent pairs; Study z point of crossing of electrons with cylinder as function of radius R for various magnetic fields B; z R

9. Pair Background and VTX Detector Compare results of GUINEA_PIG + Mokka simulation with R 2 scaling: M.B., V Telnov, Proc. 2nd Workshop on Backgrounds at MDI World Sci, 1998 Beam tests using 0.05 - 1.0 GeV e - beams at LOASIS and ALS to validate simulation. LDRD-2 response to ALS beam halo Generate library of background pair hits to overlay to hits to perform detailed simulation of occupancy, rejection and effect on patrec.

10. CMOS Pixels for ILC CMOS pixel sensors with analog, fast r/o attractive for ILC, requirements on particle extrapolation accuracy constrain pixel pitch and readout architecture, significant experience from IPHC group, applications to real experiments before ILC; Achieving < 3  m single point resolution with pixel pitch ~ 15-20  m, requires analog readout + charge interpolation: defines requirement on ADC accuracy to 4-5 bits if pedestal can be subtracted before digitisation; Power consumption constrains number of bits for ADC accuracy; Machine induced backgrounds constrain readout time; D. Grandjean/IPHC

11. ILC Vertex Tracker: Sensor Thickness (~50  m) Asymptotic Resolution Multiple Scattering + Ladder Support + Services Cooling [80 mW/cm 2 ] S/N + Cluster Size Power Dissipation [<1mW/ADC] Backgrounds + Physics Airflow removes 70-100mW/cm 2 < 0.5 mW/ADC 25 MHz r/o 25  s/512 pixel col O(1 %) occupancy ( demonstrated) [ R&D in progress] Readout Speed [25-50 MHz] Pixel Size (10-20  m) S/N + Cluster Size ADC Resolution [~5 bits] 5 hits/BX X 9 (20  m pixels)/hit = 250 k hits cm -2 Requirements and R&D Streams

12. Monolithic Pixel Sensor R&D at LBNL Analog Pixel ArchitectureBinary Pixel Architecture AMS 0.35  m-OPTO LDRD-1 (2005): 10, 20, 40  m pixels LDRD-2 (2006): 20  m pixels, in-pixel CDS 3T and SB pixels OKI 0.15  m FD-SOI LDRD-SOI-1 (2007): 10  m pixels, analog & binary pixels OKI 0.20  m FD-SOI LDRD-SOI-2 (2008): 10-15  m pixels, analog & binary pixels … Charge Interpolation [  ~ a/(S/N)] In-pixel CDS & On-chip Digitisation Fast Readout Small Pixels [  = pitch/ ] In-pixel Discr. & Time Stamping In-situ Charge Storage LDRD-3 (2007): 20  m pixels, in-pixel CDS on-chip 5-bit ADCs Chip Design: P. Denes

13. Multiple Scattering and Sensor Thickness Preserving track extrapolation accuracy to bulk of particles at low momentum requires ultra-thin sensors and mechanical support: Sensor Thickness  m amam bmbm 253.5 8.9 503.7 9.6 1253.811.7 3004.017.5 Mokka+Marlin Simulation of VXD02  need thin monolithic pixel sensor. e + e -  HZ  bb  +  - at 0.5 TeV

14. CMOS Sensor Back-thinning Back-thinning of diced CMOS chips by partner Bay Area company: Aptek. Aptek uses grinding and proprietary hot wax formula for mounting die on grinding plate: Chip mounted on PCB with reversible glue and characterized Chip removed from PCB Back-thinningChip re-mounted and re-characterized Backthinning yield ~ 90 %, chip thickness measured at LBNL after processing: “50  m” =  m, “40  m” =  m; three chips fully characterised: Thin sensitive epi-layer makes CMOS Pixel sensors in principle ideally suited for back-thinning w/o significant degradation of performance expected (especially S/N), but questions arise from earlier results; SEM Image of CMOS Pixel Chip Bulk Si Epi Si SiO + Metal

15. 40  m  Back-thinned Sensor Tests Study change in charge collection and signal-to-noise before and after back-thinning: Mimosa 5 sensors (IPHC Strasbourg), 1 M pixels 17  m pitch, 1.8 x 1.8 cm 2 surface 55 Fe Determine chip gain and S/N for 5.9 keV X rays Collimated Laser Compare charge collection in Si at different depths 1.5 GeV e - beam Determine S/N and cluster size for m.i.p. S/N CMOS sensors back-thinning feasible NIM A579 (2007) 675

16. LDRD-2 Chip LDRD-2 Chip : AMS 0.35-OPTO process ~ 14  m epitaxial layer Chip features analog pixel cell with 20 transistors in 20x20  m 2 pixel pitch providing in-pixel CDS, power cycling, different bias options, 3 and 5  m diode sizes, rolling-shutter operation with two parallel outputs of 48 x 96 pixels each. Size: 1.5 x 1.5 mm 2 6 matrices of 20x20  m 2 pixels;

17. LDRD-2: In-Pixel CDS Stored reference and pixel level with pulsed laser light: diode C ref C pixel - = pedestal subtracted signal 20  m Digitisation at end of pixel column limited in precision by speed and power dissipation: advantageous to subtract pedestal level in-pixel with correlated double sampling.

18. LDRD-2: In-Pixel CDS  = Pixel Reference Pixel Level w/ beam Example of observed response with 1.2 GeV e  electrons Pedestal

19. LDRD-2: 1.2 GeV e  Beam Test LDRD-2 tested on ALS 1.2 GeV e - beams ; Cluster Event Display Noise ~ 45 ENC

20. LDRD-2: 120 GeV p Beam Test T966 Preliminary 5  m diode T966 Preliminary 3  m diode Preliminary results @ 21 o C at 1.25 MHz 4-5 ~16 LDRD-2 tested at FNAL MTest with T966 CMOS Pixel Telescope on 120 GeV proton beam:

21. LDRD-2: 25 MHz readout test Results show no appreciable degradation of response up to maximum tested frequency of 25 MHz (r/o time 184  s) LDRD-2 1.35 GeV e  beam Cluster S/N LDRD-2 55 Fe Operate LDRD-2 at different r/o speed

22. LDRD-3 Chip LDRD-3 Chip : AMS 0.35-OPTO process, received October 2007, ADC currently under test. Third generation chip features same pixel cell as LDRD-2 with in-pixel CDS and 5-bit successive approximation fully differential ADCs at end of columns. CDS subtraction performed at digitisation level; Size: 4.8 x 2.4 mm 2 matrix of 96 x 96 of 20 x 20  m 2 pixels;

23. LDRD-SOI-1 Chip Specialised 0.15  m FD SOI process with high resistivity bulk and vias offered through KEK within R&D collaborative effort; SOI appealing to industry for low-power devices, ultra-low power stand-by; SOI process offers appealing opportunity for monolithic pixel sensors, removing limitations from commercial CMOS; Chip with 10 x 10  m 2 pixels, both 3T analog and digital architectures; (courtesy Arai/KEK)

24. TCAD Simulation p p Guardring Floating | p

25. LDRD-SOI-1 Analog Pixels: Lab Tests Significant backgating effect observed in single transistor test, expect analog chip section functional for V d < 20 V Charge collection properties tested with fast pulsed IR laser focused to 20  m: signal loss for long integration times interpreted as combined effect of backgating and leakage current:

26. LDRD-SOI-1 Analog Pixels: Lab Tests Study Leakage vs. Temperature w/ 1.384 ms integration time and CDS Study Depletion Thickness vs. SubstrateVoltage using 1060nm laser spot curves represents

27. LDRD-SOI-1 Analog Pixels: p & n Irradiation Exposure to 1-20 MeV neutrons (10 11 n /cm 2 ) shows no appreciable degradation of noise: First irradiation performed with 30 MeV protons (2.5 x 10 12 p /cm 2 ) shows evidence of charge build-up in BOX from T tests;

28. ALS 1.35 GeV e  Cluster Display LDRD-SOI-1 Analog Pixels: Beam Test V d (V) Clusters/Evt w/ beam Clusters/Evt w/o beam Signal MPV (ADC) S/N 19.70.053.311328.9 514.00.123.3924214.9 107.80.203.3131615.0 153.90.012.4530113.6 to appear in NIM A (2007) First Beam Signal on SOI Pixel Chip ALS 1.35 GeV e 

29. LDRD-SOI-1 Digital Pixels: Beam Test V d (V) Clusters/Evt w/ beam Clusters/Evt w/o beam 203.620.041.78 255.810.041.32 308.310.041.26 351.600.011.14 Digital pixel consists of 2T + comparator and latch, no internal amplification for minimum power dissipation, total 15 transistors in 10 x 10  m 2 ALS 1.35 GeV e 

30. SOI Pixel Chip

31. VTX Simulation, Reconstruction, Analysis Physics Benchmarks PixelSim Cluster Reconstruction PixelAna ALS & FNAL Beam Test Data G4/Mokka Sensor and Ladder Characterization Track Fit and Extrapolation VTX Pattern Recognition lcio Jet Flavour Tagging + CDF Vtx Fit lcio Marlin Sensor Simulation

32. Thin Pixel Pilot Telescope Layout: 4 layers of 50  m thin MIMOSA 5 sensors (17  m pixels) + reference detector; Sensor spacing: 1.5 cm 1234 beam Beam: 1.5 GeV e - from LBNL ALS booster at BTS 120. GeV p at MTest, FNAL First beam telescope based on thin pixel sensors; System test of multi-layered detector in realistic conditions.

33. TPPT at ALS Run 056 Event 001 Perform detailed studies of ILC VTX particle tracking with various, controllable, levels of track density (0.2-10 tracks mm - 2 ) under realistic conditions; TPPT Data e + e -  HZ at 0.5 TeV Distance of Closest Hit TPPT layout chosen to closely resemble ILC VTX.

34. TPPT at ALS Alignment performed using ATLAS optical survey machine and track alignment; Extrapolation Resolution on Layer 1:  =   m matches ILC requirements.  = 9.4  m Track SampleResidual (  m) 2+3 Hits Tracks 9.4 3 Hits Tracks 8.9 High Density 9.5 Low Density 9.2 NIM A579 (2007) 675

35. T-966 Beam Test Experiment at Fermilab TPPT-2 telescope: 4 layers of 50  m thick MIMOSA-5 sensors, ILC-like geometry, extrapolation resolution on DUT ~ 4-5  m Study LDRD sensors: single point resolution & sensor efficiency, response to inclined tracks, tracking capabilities in dense environment, vertex reconstruction accuracy with thin target, Validate simulation, test patrec and reco algorithms. Beam Test at FNAL MBTF 120 GeV p beam-line ( T-966 ) (UC Berkeley + LBNL + INFN, Padova + Purdue U. Collaboration)

36. 4mm Cu Target TPPT-2DUT 4-layered Telescope DUT T-966 Beam Test Experiment at Fermilab Experimental Setup 4 layers of 50  m thick MIMOSA-5 chips precisely mounted on PC boards with cut through below chip, DUT on XY stage, finger scintillator coincidence for trigger

37. T-966 at Fermilab T-966 at Fermilab First run June-July 2007: operated in various configurations: TPPT only, w/ LDRD-2, w/ target; Operated at 20 o C through forced cold air cooling, significant day/night temperature effects, need repeat track alignment daily, first preliminary results: 4 3 2 1

38. T-966 at Fermilab T-966 at Fermilab Cluster Pulse HeightCluster Pixel Multiplicity

39. Track Alignment of T966 Telescope

40. T-966 at Fermilab T-966 at Fermilab Preliminary Data 5.4  m MC 5.1  m Residuals on 1 st Plane

41. T-966 at Fermilab T-966 at Fermilab Residual on 1 st Layer vs S/N of Hits

42. e + e -  HZ  bb  +  - at 0.5 TeV ALS LOASIS MTest Track Extrapolation Resolution TPPT@ALS T966 @ MTest

43. T-966 at Fermilab T-966 at Fermilab Reconstructed 120 GeV p interaction in Cu target

44. T-966 at Fermilab T-966 at Fermilab Vertex Reconstruction for 120 GeV p interactions 4mm Cu Target Very Preliminary

45. T-966 at Fermilab T-966 at Fermilab Vertex Reconstruction for 120 GeV p interactions

46. R&D program on pixel sensors for ILC is progressing despite significant budget and manpower limitations; Various technologies/architecture being studied, mostly complementary to concurrent efforts in Europe and Asia; R&D at LBNL supported by Lab strategic funding and synergies with existing activities (STAR HFT, ATLAS pixels, pixel R&D for BES); CMOS pixel chip with in-pixel CDS and fast r/o designed and tested, new chip with in-chip 5-bit ADCs under test; First pixel chip in SOI technology successfully tested on e  beam; Experience with beam Telescope based on thin CMOS pixels for tracking and vertexing.