1. MPA-LIGHT: Design and results of a 65 nm digital readout Macro Pixel ASIC prototype with on- chip particle recognition for the Phase II CMS outer tracker upgrade A. Caratelli, D. Ceresa, R. Francisco, J. Kaplon, K. Kloukinas and A. Marchioro. PH-ESE, CERN TWEPP ‘15, Wednesday the 30 th September, 2015

2. 2 CMS was originally designed to run at Luminosity = 1 x 10 34 cm -2 s -1 HL-LHC will improve up to Luminosity = 7.5 x 10 34 cm -2 s -1 Phase II upgrades prepares CMS for HL-LHC Technical Proposal for the Phase-II Upgrade of the CMS Detector: http://cds.cern.ch/record/2020886http://cds.cern.ch/record/2020886

3. Main Outer Tracker requirements: 3 Up to pile up = 200 Contribution to Level 1 decision L1 rate = 750 KHz L1 Latency = 12.8 us Reduce Material Pixelated sensor Larger bandwidth Larger buffers P T modules New technologies + POWER - POWER

4. 4 P T module discriminates particle Pass Fail Stub Particle are discriminated according to their transverse momentum The module is composed by two sensor layers

5. Outer Tracker working principle: 5 Stub Finding Outer Tracker Front-End Stubs only Trigger-less readout: The electronics provides the stubs found at each event. Triggered readout: The electronics stores the full frame at each event.

6. 6 Stub Finding Track Find Readout Outer Tracker Front-End Tracker Back-End Stubs only Outer Tracker working principle: Dedicated talk: “Track Finding in CMS for the Level-1 Trigger at the HL-LHC”, M. Pesaresi

7. 7 Stub Finding Track Find CMS Level 1 CMS DAQ Outer Tracker Front-End Tracker Back-End CMS Level 1 accept Stubs only L1 accept rate = 750 KHz Latency = 12.8 us Full Frame Outer Tracker working principle: Readout

8. 2 x P T modules: 8 140 mm 70 mm 130 mm Z Ф 2 Strip module Strips ~ 5 cm x 90 um r > 40 cm TID ~ 40 Mrad Inner Tracker (RD53) Pixel Detector Pixel + Strip module Pixels ~ 1.5mm x 100um Strip ~ 2.5cm x 100um 20 cm < r < 40 cm TID ~ 100 Mrad

9. Pixel + Strip module exploded view 9 ShortStripASIC x 8 Concentrator IC (CIC) Data aggregation MacroPixelASIC x 16 Pixelated Layer ~ 32k pixel LP-GBT and VTRx+ Data transmission through the optical link DC-DC converters PS module is fully integrate entity Strip Layer ~ 2k strips

10. Pixel Strip module Front-End ASICs 10 MPA (1.2 cm x 2.5 cm) FEFE SRAM Data Formatting I/O Binary Readout Stub Finding Logic I/O FE Binary Readout I/O SHORT STRIP ASIC Full Frame Stubs only Strips Pixels Level-1 accept Power budget < 100 mW / cm 2 (Total for both Front-End ASICs)

11. MPA-Light: the MPA prototype 11 Analog FE circuitry in 65 nm Development of the sensor Module assembly MaPSA-Light MPA-Light

12. MPA-Light ASIC floorplan 12 16 * 100 μm 6.338 mm 2 mm 3 x 1446 μm z X Analog Pixel FE Digital Pixel Logic Analog Bias Digital Periphery Logic Bump Bonding Pads I/O Driver Row 1 Row 2 BB connection to PCB/hybrid/detector periphery WB connection to PCB/Hybrid (staggered) BB connection to detector pixels BB connection to detector GND 1.7 mm

13. MPA-Light functional description FE Hit Counter Binary Readout Sample Clock (40 MHz) 3 modes of operation available Stub finding Digital-to-analog Converters (DACs) Calibration pulses Threshold Trimming (per pixel) Input Test results are obtained without sensor i.e the input are from calibration capacitances 13 Memory Components for testing

14. Analog Front-End schematic 14 designed by J. Kaplon Preamplifier ShaperDiscriminator Current consumption < 30 uA / channel

15. Calibration DAC measurement 15 Calibration pulse [fC] 8.7 fC 0 fC 0 255 DAC code Nominal step = 0.035 fC Measured step = 0.034 fC Offset = 0.044 fC On purpose for Radiation hardness

16. Pixel Threshold spread 16 100 250 Nominal Step ~ 1.5 mV Threshold DAC Hit Counter 1000 0 0 2 Trimming DAC steps = 7.5 mV Best trimming with the 5-bits trimming DAC Pulse Injected ~ 3 fC Hit Counter

17. Gain and Noise from S-curves (1) 17 0.35 fC … 1.05 fC 60200 Nominal Step ~ 1.5 mV Threshold DAC 1000 0 Optimization region Calibration pulse amplitudes Hit Counter 2.45 fC

18. Gain and Noise from S-curves (2) 18 0.35 fC2.25 fC Calibration pulse amplitude Threshold [mV] 30 mV 190 mV Hit Counter 1000 120 140 Threshold DAC 0 80 sigma(cerf) = ENC mean(cerf) = Threshold Complementary error function fitting

19. MPA-Light functional description FE Hit Counter Binary Readout Sample Clock (40 MHz) 3 modes of operation available Stub finding Digital-to-analog Converters (DACs) Calibration pulses Threshold Trimming (per pixel) Input Test results are obtained without sensor i.e the input are from calibration capacitances 19 Memory Components for testing

20. Binary readout allows FE studies: 20 3.4 fC 2.2 fC 1.1 fC Peaking time ~ 24 ns 0 ns 140 ns 0 mV 310 mV Peak Gain ~ 91 mV/fC Shaper Output [mV] Injection time [ns] Shaper output for different charge 1 fC 9 fC ΔWalk Time [ns] Max delay < 10 ns Injected Pulse [fC] FE walk time (Threshold = 0.5 fC) 0 ns Simulations value: Time walk: < 14 ns from 0.5 fC to 12 fC Peaking time = 24 ns

21. 000000 110 010 100 110 Z X From Binary readout MPA-Light digital logic testing 1. No Processing mode: Used to test Binary readout and Pixel Clustering 21

22. 000000 000 010 100 000 Z X From Binary readout + Pixel Clustering MPA-Light digital logic testing 1. No Processing mode: Used to test Binary readout and Pixel Clustering 22

23. 000000 000 010 100 000 Z X From Binary readout + Pixel Clustering Centroid List X = 3, Z = 1 X = 2, Z = 3 MPA-Light digital logic testing 1. No Processing mode: Used to test Binary readout and Pixel Clustering 2. Data Processing mode: Used to test Encoding and Stub Finding Logic 23

24. 000000 000 010 100 000 Z X From Binary readout + Pixel Clustering Centroid List X = 3, Z = 1 X = 2, Z = 3 Stub List X=3, Z=1, B=0 X=2, Z=3, B=-1 or 010000 MPA-Light digital logic testing Tested with pattern from FPGA 1. No Processing mode: Used to test Binary readout and Pixel Clustering 2. Data Processing mode: Used to test Encoding and Stub Finding Logic 24 Further details on the Stub finding logic: http://iopscience.iop.org/article/10.1088/1748-0221/9/11/C11012http://iopscience.iop.org/article/10.1088/1748-0221/9/11/C11012

25. 000000 000 010 100 000 Z X From Binary readout + Pixel Clustering 010100 Centroid List X = 3, Z = 1 X = 2, Z = 3 Stub List X=3, Z=1, B=0 X=2, Z=3, B=-1 or 010000 MPA-Light digital logic testing Tested with pattern from FPGA 1. No Processing mode: Used to test Binary readout and Pixel Clustering 2. Data Processing mode: Used to test Encoding and Stub Finding Logic 3. Strip Emulator mode: Tested with oscilloscope 25

26. Total Ionizing Dose (TID) with X-ray 26 PS module TID < 100 Mrad 0 Pre rad value -15 % Total Ionizing dose [log TID] 150 Mrad Annealing - 11 % Threshold DAC variation with TID 0 100 Mrad ∆ Threshold Step [%]

27. Conclusion and future plans MPA-Light fully functional MaPSA-Light ready MaPSA-Light Testing MPA & SSA design Final size MPA and SSA 27

28. Thanks to all the CMS TRACKER PHASE II ELECTRONICS TEAM 28 Davide Ceresa, A. Caratelli, R. Francisco, J. Kaplon, K. Kloukinas and A. Marchioro. PH-ESE-ME, CERN TWEPP ‘15, Wednesday the 30 th September, 2015

29. Backup slides 29 Davide Ceresa, PH-ESE-ME, CERN TWEPP ‘15, Wednesday the 30 th September, 2015

30. 30 Reduced thanks to: Bend bits reduction Tight Stub threshold Different LP-GBT transmission mode Good stub losses lower than 0.5% in all the tracker at Pile Up 200 Stub transmission to tracker back- end is clearly critical for the first barrel layer simulation and studies by S.Viret Tracker Back-end data transmission

31. Tracker power budget is limited 31 Working temperature cooling: ~ -30C Total Power Allocated per 16 MPAs and SSAs: 4W Total Power Allocated per MPA + SSA: 250 mW Rough Power Estimation: Analog70 mW L1 Memory70 mW SSA40 mW Remaining70 mW I/O Clock Distribution Data Transport Stub Finding Logic L1 Data Logic Output Interface

32. Powering reference scheme 32 0.8 – 1V used to power digital logic which can work also at low voltage slide and studies from G. Blanchot, F. Faccio and S.Michelis

33. Stub Finding logic efficiency results 33 Module efficiency Layer Efficiency Layer efficiency with interconnection VertexZ -Z

34. Stub Finding logic efficiency results 34 X V Module A Module B VertexZ Recovered Without an interconnect technology (ex: TSV) between the two sides of the module, tracks crossing the middle will not be identified as stubs

35. Stub Finding logic efficiency results 35 V V Module A VertexZ V Tilted layout solves the problem and decrease the number of modules, but complicates mechanics

36. Flipped MaPSA concept 36 Only bump bonding in MPA design No extra material between sensors Better cooling of MPA Digital IO through sensor periphery Temperature gradient across the sensor surface Larger sensor can create problem in final production STRIP SENSOR MPA SSA MPA SSA EXTENDED PIXEL SENSOR Cooling BASELIN E STRIP SENSOR PIXEL SENSOR SSA MPA Cooling PROPOSA L

37. MPA-Light test system overview 37 Power Supply Ethernet Cable MPA-Light Test system controlled by Python routines Communicates with IP bus Interface Board Voltage and Current generator and monitors designed for the CLICpix readout by Szymon Kulis FPGA Handle configuration, readout and control the interface board Load board Exchangeable board for the ASIC wire bonding and decoupling developed by A. Caratelli

38. Analog Front-End simulation results 38 designed by J. Kaplon Other simulation results: Gain from S curves: 85 mV/fC Time walk :< 14 ns with threshold at 0.5 fC and signal from 0.75 to 12 fC Noise(Worst case): > 20) Spread 90 mV pk-pk Peaking time 24 ns Montecarlo simulations 100 runs for 2.5 fC

39. Binary readout allows FE studies 39 40 MHz Clock Hit detector output 27 28 Discriminator Output Shaper Output Changing the calibration injection point and using the synchronous readout we can characterize the shaper of the analog FE Observing when the time stamp change we can extract the rising time of the shaper from zero to the set threshold Threshold

40. Service Board with Staged DCDC scheme 30/SEP/2014G. Blanchot, F. Faccio, S. Michelis - 2S and PS Powering Meeting Input power: low profile Molex Picoblade 2 poles connector (stands our current rating). The filters will stay out of the shield area, must be on sides. Wirebond based IO implemented so far. The same low mass ECCA based coil is used for the 3 converters. The new LV DCDCs still based on teh FEASTMP geometry. However we can consider a smaller package for this chip. The 3 DCDC stages can be fitted in the available board space without excessive compromise. Wirebonds Input Filters 16V caps FEASTMP LV caps New DCDCs Filters Wirebonds

41. PS module Forum 2014: Tilted Barrel for CMS Phase 2 Upgrade 11 12 9 1 2 3 4 5 8 1.Silicon strip sensor 2.Silicon pixel sensor 3.Macro-Pixel ASIC (MPA) 4.Al-CF sensor spacer 5.CFRP base plate 6.FE Hybrid 7.Opto-Link Hybrid 8.Power Hybrid 9.Short-strip ASIC (SSA) 10.Concentrator IC (CIC) 11.Hybrid CF support 12.Al-CF Hybrid spacer 6 7 10 11 12 Support and cooling via a large-area base plate

42. 42 More realistic tilted geometry Forum 2014: Tilted Barrel for CMS Phase 2 Upgrade Z = 0 Short cylindrical section in the center Constant tilt angle in several successive rings o Helps avoiding clashes o Also, reduces support structure variants.

43. 43 Material budget full tracker Forum 2014: Tilted Barrel for CMS Phase 2 Upgrade S. Mersi at al., Performance of Tilted Inner Barrel, CMS Upgrade Workshop 1 April 2014