1. PSI - Jul. 18th, 20071 Status of the electronics and DAQ systems of the MEG experiment

2. PSI - Jul. 18th, 20072 Electronic chain 216 630 Active Splitter 1:1 4:1 Active Splitter 1:1 4:1 Active Splitter 1:1 4:1 Ramp 60120 Pre-Amp 8:1 PMT LXe HV PMT lateral front TC HV APD PMT bars fibers DC HV Wires Strips Pre-Amp 576 1156 atten DRS 5 crates 512 Hit registers 4 boards Trigger 32 3 crates Aux. devices INFN-Le INFN-Pv PSI INFN-Ge

3. PSI - Jul. 18th, 20073 5 crates DRS Hit registers Trigger 3 crates 20 MHz clock Trigger signal Event number Trigger type Trigger Start Busy Error  E5 area ‘counting room’ PC (Linux) Front-End PCs Gigabit Ethernet On-line farm PC (Linux) storage PC (Linux) Event builder Type3 1 crate clock start stop sync Ancillary system DAQ and control Run start Run stop Trigger config Main DAQ PC PC (Linux) INFN-Pi PSI INFN-Ge INFN-Pi

4. PSI - Jul. 18th, 20074 HV system Active down regulation of an external HV supply 4 different requirements Lxe: 1000V, 100 uA TC bars: 2400V, 1 mA TC curved: 500V, <1 uA DC: 2400V, ~1 uA 10 chn per board - 180 chn per crate 24-bit ADCs for high accuracy (20mV) Read out every 4 seconds of 900 chn Commercial HV supplies installed Mass production completed Installation completed in January ‘07 Tests –laboratory tests –60 chn for TC ran stably for 2 weeks in December The system is ready

5. PSI - Jul. 18th, 20075 Splitter 4÷1 Trigger or DRS Power Inputs Single coaxial cable (RG178–9m) Negligible crosstalk 1÷1 DRS output high bandwidth High density twisted pairs crosstalk ~ 0.6% 1÷1 trigger or Type3 output Standard twisted pairs cable

6. PSI - Jul. 18th, 20076 Splitter Summary Splitter –16 inputs –16 output 1÷1 differential 400 MHz –16 output 1÷1 differential 100 MHz –4 outputs 4÷1 attenuated differential 100 MHz –Noise <1 mV rms –Cross-talk ~0.6% with LXe signals –Common calibration levels from backplane Installation –Completed in September 06 Cables –All cables ready at PSI –Only TC cables installed during December 06 run Test –Satisfactory test during December 06 run The system is ready

7. PSI - Jul. 18th, 20077 TC APD-preamplifiers APD pre amplifiers First prototype with problems on IC and cross talk Second prototype design and test completed Mass production and test completed Assembly and test completed System delivery in Aug ’07 (Glued to the TC fibers)

8. PSI - Jul. 18th, 20078 TC APD hit registers Mezzanine board host on the PSI GP-VME boards (the same boards used for DRS) Design, production and test completed The system consists of 6 VME boards System delivery Aug ‘07 (with the detector)

9. PSI - Jul. 18th, 20079 TC Ramp PMT ramp generator Design of the final boards completed Mass production in progress system delivery 8 boards Aug 07

10. PSI - Jul. 18th, 200710 Trigger Boards Type1 Front end Type2 Ancill

11. PSI - Jul. 18th, 200711 Trigger system status Installation -The entire system has been installed in Jul 06. -Active sub-detectors cabled in Nov 06 -Pedestal and TC triggers provided during Dec 06 test run -Integration of the trigger and DAQ Nov-Dec 06 The system is ready Configuration firmware -Baseline Version 3 ready for download Jul 07 Scaler readout (implemented for Type 1.3 @Run06) Memory space arrangement (faster read-out) Revised trigger list Trigger tree –Increased number DCH wire sum (individual inputs for each end) –Cosmic ray counters Analysis software –Base analysis tools available –Trigger parameters evaluation and download, under development –Monitoring and efficiency evaluation tools

12. PSI - Jul. 18th, 200712... 14 boards 14 x 48 Type1 16 4 LXe front face (216 PMTs) 2 boards... 5+5+2 boards 9 x 48 Type1 16 4 LXe lateral faces back (216 PMTs) 4 in 1 lat. (144x2 PMTs) 4 in 1 up/down (54x2 PMTs) 4 in 1 1 board Timing counters curved (512 APDs) 8 in 1 bars (30x2 PMTs) 1 board 2 x48 Type2... 9 boards 9 x 48 Type1 16 4 4 boards 2 x 48 Type1 16 4 Drift chambers 64 channels 2 x48 1 x48 Type1 2 x48 16 Auxiliary devices 16 channels The trigger tree Type2 4 x 48 Type1 16 CR counters 32 channels Type1 16

13. PSI - Jul. 18th, 200713 Trigger list (1) QT H QT L MeV DW W DW N LXe charge e + -  direction e + -  timing trig.# name conditions 0 MEG Q SUM > QT H && D < D N && |  T| < TW N 1 MEG-Q Q SUM > QT L && D < D N && |  T| < TW N 2 MEG-D Q SUM > QT H && D < D W && |  T| < TW N 3 MEG-T Q SUM > QT H && D < D N && |  T| < TW W 4 RD-narrowQ SUM > QT L && |  T| < TW N 5 RD-wide Q SUM > QT L && |  T| < TW W

14. PSI - Jul. 18th, 200714 Trigger list (2) trig.# name conditions 6  0 Q SUM > QT H && Q NaI > Q N && |  T| < TW N 7  0 -NaI Q SUM > QT L && |  T| < TW N 8 NaI Q NaI > Q N 9 LXe-highQ SUM > QT H 10LXe-lowQ SUM > QT L 11CWQT L < Q SUM < QT H 12 neutron Q patch < QT patch && Q i < QT i 13  pulse-shape &&Q SUM QT WIRE 14laser Q LAS > QT LAS 15led

15. PSI - Jul. 18th, 200715 Trigger list (3) trig.# name conditions 16 michel N DC  4 && Q L > Q T && Q R > Q T && (Q L +Q R ) > Q TS 17 DC track out N DC  4 && I out 18 DC track N DC  4 19 DC + CR single DC && CR 20 DC 21 CR 22 TC Q L > Q T && Q R > Q T && (Q L +Q R ) > Q TS 31 pedestal internally generated random triggers

16. PSI - Jul. 18th, 200716 Cyclic buffers Diff. driver FADC Cyc. buff Proces. Algor. LVDS Tx Cyc. buff Type1 FPGA Cyc. buff Proces. Algor. LVDS Tx Cyc. buff Type2 FPGA LVDS Rx Cyc. buff Proces. Algor. LVDS Tx Cyc. buff Type2 FPGA LVDS Rx Type1 layer Type2 layer Final Type2 Analog inputs Trigger output

17. PSI - Jul. 18th, 200717 Monitoring: TRG Waveform 512 channels (5120 ns) 10 FADC bit data Range 0 V --> 1V 20 MHz Bandwidth Typical pulse  400 mV Baseline Fluctuation  1 mV (s  0.4 mV) T (ns)

18. PSI - Jul. 18th, 200718 Monitoring: system operation Periodic monitor of the system parameters performed automatically in the DAQ Clock locking Synchronous operation LVDS data transmission Computer busy Rates (trigger, channel) Automatic alarms in case of failure

19. PSI - Jul. 18th, 200719 Detector monitoring: rates Rate of individual channels (independent of trigger)

20. PSI - Jul. 18th, 200720 Efficiency: tools 1.Cyclic buffers -dump-mode used to take 5us depth snapshot of the trigger status for monitoring, debugging and efficiency evaluation (PMT signals, physical quantities estimators: charge, time, amplitude, position, patterns …) -source-mode used to process simulated events as well real recorded events 2.Trigger –Prescaled unbiased triggers simultaneously acquired with meg events 3.Algorithm emulators –Simulation of FPGA algorithms with Xilinx tool intensively used –Emulation by means of c++ code in progress 4.Simulated data –Meg events –Calibration events

21. PSI - Jul. 18th, 200721 DRS2 PSI GVME Board FPGA with 2 Power-PC Mezzanine boards

22. PSI - Jul. 18th, 200722 DRS System Optical fiber Back-end PC Off-line cluster Ethernet Front-end PC All channels equipped with DRS2 2636 channels 1024 cells per channel 0.5 - 2.5 GHz sampling speed After calibration pedestal noise at 0.5 mV RMS

23. PSI - Jul. 18th, 200723 DRS2 online calibration mV ADC counts / 10 The pedestal is dependent on the cell number Need of individual pedestal value for each bin The non-linear response function depends on the cell number Need of different response functions for each bin –Measure V in – ADC out characteristics with precise DC power supply at the DRS2 input –Fit and store parameters online –Write on disc linearized, pedestal subtracted samples

24. PSI - Jul. 18th, 200724 DRS3 status 50 prototypes of DRS3 available for test

25. PSI - Jul. 18th, 200725 DRS3 linearity U in (V) U out (V)

26. PSI - Jul. 18th, 200726 DRS3 nonlinearity Point deviation from linear interpolation for five arbitrary cells 30 deg. C 50 deg. C Integral nonlinearity is below 1mV with only one offset per cell used for correction Output changes by ~1mV in 20 deg. C --> T c = 50 ppm

27. PSI - Jul. 18th, 200727 DRS3 summary No dangerous temperature instability Readout speed increased 16 MHz (DRS2) -> 33 MHz “Region Of Interest” – Readout mode works Master clock signal (LVDS) can be digitized differentially  improvement in clock signal Plan: –VME boards with DRS3 test in July 2007 –Order engineering run after all tests have been finished –Get chips in ~December, but not in time for this year’s beam time

28. PSI - Jul. 18th, 200728 Auxiliary digitizer:Type3 Modified Type1 boards to produce an auxiliary digitization of the LXe signals

29. PSI - Jul. 18th, 200729 Auxiliary digitizer status Higher input capability (32 channels), no LVDS transmission 612 PMTs on LXe lateral+back sides  20 boards Prototype tests: Jan 07 –Bit-stream downloading through VME  –Control signal (CLK, SYNC, START, STOP) distribution  –FADC digitization and storage  –RAM readout  Production: Apr 07 Tests: May 07 Installation: Aug 07

30. PSI - Jul. 18th, 200730 DAQ 80 GB System Disk RAID 1 (Mirror) /home/meg 1.2 TG Data Disk RAID 5 80 GB System Disk RAID 1 (Mirror) 80 GB System Disk RAID 1 (Mirror) Back-End Front-End #1 Front-End #2... NFS VME-Interface SC-FE Gigabit Switch

31. PSI - Jul. 18th, 200731 Multi-threading model VME Transfer Thread Calibration Thread Calibration Thread Calibration Thread Calibration Thread Collector Thread VME Round-Robin distribution Network Zero-copy ring buffers

32. PSI - Jul. 18th, 200732 DRS Readout rate Optimal readout rate of DRS full waveforms with 4 calibration threads: 30 events/s During Dec 06 run max readout at 7 events/s –Double event readout –Code optimization –Single calibration thread

33. PSI - Jul. 18th, 200733 DRS Readout rate Assuming 50% occupancy Zero suppression done on the front-end Max transfer rate at 50 events/s –Hits the VME transfer speed Much larger than the expected maximum trigger rate of 20 events/s

34. PSI - Jul. 18th, 200734 Trigger readout rate Type 3 boards (32 ch/board) –Standard 2EVME A32, D64 Readout –For 1 cycle T AS  650  s/board (  v  50 MB/s) –20 boards/crate: 70 events/s  (%Live)  80% @ trigger rate = 20 s -1 Type 1 (16 ch/board) & Type 2 (18 ch/boards) –Custom 2EVME A32, D32 Readout (no access to A31-A0 during data broadcast) –For 1 cycle T AS  1300  s/board (  v  25 MB/s) –20 boards/crate: 60 events/s  (%Live)  75% @ trigger rate = 20 s -1

35. PSI - Jul. 18th, 200735 Higher DAQ rate Higher rate is considered only for calibration events 50 Hz full waveform readout hits VME transfer limit (83 MB/sec) VME transfer size can be reduced by doing zero- suppression and ADC/TDC analysis on VME side –Use embedded Power-PC CPUs (C-code) –Use FPGA (VHDL-code) Tools –Basic zero-suppression in VME in late 2007 –ADC/TDC analysis in VME later in summer, need input from sub-detector groups –Possibility of reaching 100 Hz

36. PSI - Jul. 18th, 200736 DAQ rate vs. amount of data DAQ speed is not a limiting factor The total data size needs solution: –30 Hz is maximal VME speed for full waveforms → >270 MB/sec –Data transmission limit is 20 MB/sec (=250TB/year) → need online reduction 10x –Storage limit is 30 TB/year → need offline reduction 8x

37. PSI - Jul. 18th, 200737 Online data reduction The factor 10 data size reduction obtained within the DAQ system: Level 3 trigger in the Event Builder task: –Fast linear fit of the LXe energy with trigger wfms –Presence of an e + with a minimal momentum using DC information Waveform data compression –Zero suppression –ADC/TDC like data for calibration –Waveform rebinning

38. PSI - Jul. 18th, 200738 Data size reduction Possible algorithms for data size reduction Zero suppression: hit if max.ampl. > n x  (baseline) Readout window at the trigger time Pile-up flag: Zero-crossings of first derivation Re-binning of signal tail4:1, 8:1 ADC for calibration events: Numerical integration of signals over baseline 0.5 ns bins 4 ns bins

39. PSI - Jul. 18th, 200739 Conclusions Splitters: installed, operational, expected performances, test in Dec 06 Fiber preamp: problem with an IC fixed, test passed, mounted on the TC detector, installation in Aug 07 Hit registers: mezzanine boards produced, FPGA firmware ready (PSI GPVME board), installation in Aug 07 Trigger: installed, operational, built-in debugging and control tool, need tuning after detector turn on, test in Dec 06

40. PSI - Jul. 18th, 200740 Conclusions DRS2: installed, operational, good for timing, temperature dependence, usable with DC DRS3: prototype test phase, final solution, not available in 2007 Aux digitizer: production problem solved, prototype test completed successfully, ready for 2007 run DAQ: installed, operational, good performances, test in Dec 06 run The electronics and the DAQ systems are expected to be ready for the 2007 run

41. PSI - Jul. 18th, 200741 Rack space

42. PSI - Jul. 18th, 200742 Trigger reminder Digital approach –Flash analog-to-digital converters (FADC) –Field programmable gate array (FPGA) trigger observables –  energy, direction and time (Lxe calorimeter) –e + time and approx. direction (Timing Counters) Expected rate –For 10 8 muon stop rate

43. PSI - Jul. 18th, 200743 All triggers can be: masked prescaled (up to 32 bits) Trigger features Other information Type 1 100 MHz, 5  s depth, 10 bits, waveforms for all channels Single rate for each channel Type 2 Rate for each trigger type Event Counter (hardware distributed to the DRS boards) Trigger pattern (hardware distributed to the DRS boards) Live Time and Dead Time

44. PSI - Jul. 18th, 200744 Trigger efficiency: example events associated with the TRG STOP ( ~1  s delay) ss ss low intensity (slit = 10%) high intensity (slit = 100%) –Extract pulses for – “Trigger” events – “Unbiased” events (out of trigger window and with 10 mV threshold)

45. PSI - Jul. 18th, 200745 Trigger efficiency: TC charge Unbiased Trigger N pe Landau peak for e+ Secondary particles rescaled by R pulse  T  = N T /N U  almost full efficiency at Landau peak (~6MeV, ~500pe) Interpolation by erf function

46. PSI - Jul. 18th, 200746 DRS2 primer Need of external buffer and FADC

47. PSI - Jul. 18th, 200747 DRS2 Temperature Dependence T [º C] V out [V] DRS2 has a marked dependence on the temperature T c ~ 1.4 % / ºC