1. Computer Architecture Lecture 3 Combinational Circuits Ralph Grishman September 2015 NYU

2. Time and Frequency time = 1 / frequency frequency = 1 / time units of time millisecond = 10 -3 second microsecond = 10 -6 second nanosecond = 10 -9 second picosecond = 10 -12 second units of frequency kiloHertz (kHz) = 10 3 cycles / second megaHertz (MHz) = 10 6 cycles / second gigaHertz (GHz) = 10 9 cycles / second 9/14/15Computer Architecture lecture 32

3. Today’s Problem A typical clock frequency for current PCs is 2 GHz. What is the corresponding clock period? (a) 200 ps (b) 500 ps (c) 2 ns (d) 5 ns 9/14/15Computer Architecture lecture 33

4. Solution Frequency = 2 GHz = 2 * 10 9 Hz Period = 1 / frequency = 1 / (2 * 10 9 ) sec = (1 / 2) * (1 / 10 9 ) sec = 0.5 * 10 -9 sec = 0.5 ns = 500 * 10 -6 sec = 500 ps 9/14/15Computer Architecture lecture 34

5. Assignment #1 various short questions about combinational circuits 9/14/15Computer Architecture lecture 35

6. Design tools see lecture outline 9/14/15Computer Architecture lecture 36

7. Propagation Delay delay of individual transistor -- how fast it can switch -- determined by physical factors (e.g., size) speed of transistor determines speed of gate 9/14/15Computer Architecture lecture 37 time voltage in out

8. Propagation Delay the propagation delay (speed) of a combinatorial circuit is the length of time from the moment when all input signals are stable until the moment when all outputs have stabilized 9/14/15Computer Architecture lecture 38

9. Propagation Delay propagation delay of a combinatorial circuit can be determined as longest path (in number of gates) from any input to any output delay=2 9/14/15Computer Architecture lecture 39

10. A Very Rough Estimate After transistor switches, it has to charge output wires – this may be a large part of total delay – so assuming all gate delays are the same produces a very rough estimate of circuit delays – but is good enough for understanding principles of circuit design so we will make that assumption in this course 9/14/15Computer Architecture lecture 310

11. Fan-in sum-of-products form suggests any combinatorial function can be computed in 3 gate delays (one delay for inverters, one for ANDs, one for OR) 9/14/15Computer Architecture lecture 311

12. Fan-in but gates are limited in their fan-in (number of inputs a gate has) 9/14/15Computer Architecture lecture 312

13. Fan-in for example, if fan-in is f, it takes log (base f) n gate delays to OR or AND together n inputs log 2 8 = 3 gate delays 9/14/15Computer Architecture lecture 313

14. Adders The simplest case: adding two one-bit numbers Sum = A xor B Carry = A and B 9/14/15Computer Architecture lecture 314 ABSumCarr y 0000 0110 1010 1101

15. n-bit Adder adding multi-bit numbers: – have to keep track of a carry out of one bit position and into the next position to the left 0 0 1 1 + 0 0 0 1 0 1 0 0 9/14/15Computer Architecture lecture 315

16. n-bit Adder Do this with full adders, which have 3 inputs: A, B, and C in, and 2 outputs, Sum and C out. 9/14/15Computer Architecture lecture 316 ABCinSumCout 00000 00110 01010 01101 10010 10101 11001 11111

17. Full Adder We will show the connections of the full adder as follows: 9/14/15Computer Architecture lecture 317 A Sum Cout B Cin

18. n-bit Adder Then we can draw a 3-bit adder like so: 9/14/15Computer Architecture lecture 318 Cout Cin A2 B2 A1 B1 A0 B0 Sum0 Sum2 Sum1

19. n-bit adder: delay ripple-carry adder: carry ripples from bit 0 to high-order bit total delay (for large n) = n * delay(Cin  Cout) 9/14/15Computer Architecture lecture 319

20. Signed Numbers So far we assumed the bits represent positivve numbers: 9/14/15Computer Architecture lecture 320 0 0 00 0 0 11 0 1 02 0 1 13 1 0 04 1 0 15 1 1 06 1 1 17

21. Signed Numbers We could use some of the bit patterns to represent negative numbers, like so: 9/14/15Computer Architecture lecture 321 0 0 00 0 0 11 0 1 02 0 1 13 1 0 0-0 1 0 1 1 1 0-2 1 1 1-3 sign and magnitude

22. Signed Numbers Or like so: 9/14/15Computer Architecture lecture 322 0 0 00 0 0 11 0 1 02 0 1 13 1 0 0-4 1 0 1-3 1 1 0-2 1 1 1 two’s complement

23. Signed Numbers Or even like so: 9/14/15Computer Architecture lecture 323 0 0 00 0 0 11 0 1 02 0 1 13 1 0 04 1 0 15 1 1 0 1 1 1-2

24. Why do we prefer two’s complement? 9/14/15Computer Architecture lecture 324

25. Why do we prefer two’s complement? Can use same logic as for unsigned addition 9/14/15Computer Architecture lecture 325

26. Computing two’s complement Given representation of v, how to compute representation of –v ? 9/14/15Computer Architecture lecture 326

27. Computing two’s complement Given representation of v, how to compute representation of –v: flip every bit in representation of v add 1 9/14/15Computer Architecture lecture 327

28. Computing two’s complement 9/14/15Computer Architecture lecture 328 Cout Cin 0 0 1 Acomp0 Acomp2 Acomp1 A2 A1 A0

29. Subtracting B – A = B + (-A) 9/14/15Computer Architecture lecture 329 Cout Cin 0 0 1 Acomp0 Acomp2 Acomp1 A2 A1 A0 B2 B1 B0

30. Can we simplify this? 9/14/15Computer Architecture lecture 330

31. Subtracting: B – A = B + (-A) 9/14/15Computer Architecture lecture 331 Cout Cin B2 B1 B0 (A-B)0 (A-B)2 (A-B)1 A2 A1 A0 1