1. ITRS ERD/ERM in KOREA

2. 2 ITRS ERD/ERM Korean Chapter Memory Committee IndustryAcademia Committee I.-S. Yeo (Samsung) S.W. Cheong (Hynix) T.W. Kim (Sejong U) H.C. Sohn (Yonsei U) J.I. Hong (Yonsei U) C.S. Hwang (Seoul Natl U) H.S. Hwang (KJIST)

3. 3 Memory Devices Volatile Memory Non-volatile Memory Polarization change Charge Trap Resistance change Classification of Memory Devices DRAM SRAM SONOS FLASH FRAM RRAM Magneto- Resistance changes Phase- dependent Resistance changes 1 2’ 2 V1V0 1’ “0” ” I oxide Interface or bulk Resistance changes Charge-based Programming & Reading Current-based Programming & Reading MRAM PRAM Ref.: Samsung

4. 4 Nanomechanical Memory Fuse- Antifuse Memory Ionic Memory Electronic Effects Memory Macro- molecular Memory Molecular Memories Storage Mechanism Electrostatically- controlled mechanical switch Multiple mech. Ion transport and redox reaction Multiple mechanisms Multiple mech. Not known Cell Elements 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R Device Types 1) Nanobridge / cantilever 2) telescoping CNT 3) Nanoparticle M-I-M (e.g., Pt/NiO/Pt) 1) cation migration 2) anion migration 1) Charge trapping 2) Mott transition 3) FE barrier effects M-I-M (nc)- I-M Bi-stable switch ITRS ERD/ERM (Emerging Memory) Ref.: ITRS08

5. 5 Next NVM Projects in Korea Ref.: Ministry of Knowledge and Economy 2008. 06  Next Nonvolatile Memory Projects 1. Period: 2005~2011, 7 years 2. Total Budget: 50.5B K ₩ (42M US$, Exchange Rate=1200K ₩ ) 3. Focus on Developing New NVM for High Density Memory 3D NFGM J.H.Lee (Kyungbuk U) Nanodot, 3D- device TBE NFGM W.J. Jo (Kwangun U) Tunel Barrier Resistive PoRAM J.K. Park (Hanyang U) Organic, Metal cluster Ferro FET C.M. Park (Yonsei U) Organic/ Inorganic FET Chalcogenide RAM B.K. Jeong (KIST) Chalcogenide Material ReRAM H.S. Hwang (KJIST) Cell, Integration Perpendicular STT-MRAM J.K. Park (Hanyang U) Planning (will start ’09) SupervisionHanyang Univ (J.K. Park) NFGM STT-MRAMPoRAM ReRAM

6. 6 Highly Reliable ReRAM !! Binary oxide Multilayer binary oxide PerovskitePMC Material Develop Materials RS Mechanism Memory cell Reliability / Uniformity Scalability (~50nm) Cell array integration <100nm unit process 32 x 32 cell array Array characterization Strategic Approach (ex.: ReRAM) Epi-Oxide Charact. Doped binary oxide Modeling Fundamental Study Unit cell & cell array develop (KJIST) Industry: Feedback, Tech. Support Ref.: Hwang

7. 7 Summary of current status (ReRAM) ITEM Measure Condition 1 st screen Spec. 2 nd Spec. Cu:MoO x /GdO x CuC R.M /LCMO(PCM O) Switching I sw Current @ Reset <1 mA<100 uA<300uA <100uA V sw Voltage @ Set, Reset <3.0 V<2.0 V<±2V<±1V<±3V R off /R on R off @0.2V / R on @0.2V >100>1000>1000 @0.2V >100 @0.1V >300 @-1V Distrib. V sw (Δ/σ) Voltage @ Set, Reset (>30 point) 2.510 5.15 (50samples) 8.3 Hysteresis type ΔR (@LogR) / σ (@LogR) R on, R off @0.2V (>30 point) 520 9.4 (50samples) 4.9>10 Reliab. Retention On↔Off change after thermal stress (>30 point) No Fail bit After 125 ℃ /10 h No Fail bit after 85 ℃, 10 y 85 ℃, 10 year (1-sample) 125 ℃ / >10 4 sec (1-sample) 85 ℃ / >>10 4 sec (1-sample) Endurance 10 ms pulse >1E2>1E4>2E4>1E3 ACT sw Time Delay <10 uS<100 nS<1usec-<3usec Cell Array- Number of Cell -- Nanoimprint 8X8 cell array E-beam litho 8X8 cell array - Nanoimprint 32x32 cell array Sub 50nm Scale device 4 inch wafer process Unit cell process  Mass production Ref.: Hwang

8. 8 Hybrid memory in dual layer Cu:MoO x /GdO x stack Schematic diagram Filament switching Ionic switching DC I-V sweep No switching for Pt/Cu:MoO x /Pt Hysteretic bipolar switching No Area dependence Cycles >10 3 by DC Device performance Cell Array & 4” process ∆V=2.15 ∆V/σ=6.8 6 ∆V/σ=5.1 5 Ref.: Hwang

9. 9 Redox / oxidation memory Sm / LCMO stack Motivation DC I-V sweep Device performance Analysis of Switching mechanism S. Muraoka et al, IEDM2007 Unity Semiconductor, US0171200 Ref.: Hwang

10. 10 PMC memory Cu-C memory Motivation Schematic diagram & DC I-V sweep Device performance Improvin g pulse switching Low operation voltage Retention @ high temp Porous Small radius Ref.: Hwang

11. 11 Nanodevice using CuC (with Hynix) Wafer provided by Hynix Schematic diagram DC I-V sweep Pulse switching Cu-C Si sub TiN W Thermal oxide NIT TE TiN Area dependence Summary materialsCuC/Cu TE typebipolar Contact area0.00176~0.00436μm 2 On/off ratio>3 order Set/Reset V+3/-2V Pulse switching +5V 10μs /-2V 1 μs 44nm58nm Split 42~66nm Ref.: Hwang

12. 12 TEM Analysis on LRS/HRS spot 30 nm HRS LRSHRS PCMO 30 nm 10 nm ElementWeight%Atomic% O K7.9123.52 Al K35.5762.70 Pt L56.5113.78 Totals100.00 Element 1 Weight%Atomic% O K42.5157.53 Al K50.3240.38 Ca K1.500.81 Mn K1.710.67 Pr L3.970.61 Totals100.00 300k 10 nm HRS – Robust AlO x EDX Analysis PCMO Pt LRS FIB Milling Tilt Pt PCM O Pt Evidence for the switching models Pt Interface sample for TEM analysis OFF Sm LCMO Mo O 2- ON AlO x O 2- OFF Al PCMO O 2- ON O 2- Pt Oxidation Reduction Ref.: Hwang

13. 13 Overview of ReRAM Operation Principle (Unipolar) - Resistance Change by Filament Formation/Rupture - On-states When Filament Formed - Off-states When Filament Rupture Merits - Low-cost, Simple Processes - Relatively Easy 3-D Stacking Obstacles - Unclear Mechanism - Use of Metastable Materials Electrode Oxide Diode, ND Cross Point Array3D Stacking Strategy for Low-cost, High-density Memory Ref.: Samsung

14. 14 Summary  Why ReRAM? Scalability potential (No charge-limited)  Operation at sub 20nm ?? 4F2 Cross-point structure  Requires Control Elements !! 3-D stacking  Cost effective ??  Requirements for ReRAM CMOS compatibility  Non-noble electrode Control elements: Diode for unipolar switching  Enough drive current ?? Threshold switch (varistor) for bipolar switching  Exist ?? Multi-bit operation  Requires large P/E window, very good distribution Selection Rule for ReRAM ??