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Presented by Anas Mazady, Cameron Fulton, Nicholas Williams University of Connecticut Department of Electrical and Computer Engineering Thursday, April.

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Presentation on theme: "Presented by Anas Mazady, Cameron Fulton, Nicholas Williams University of Connecticut Department of Electrical and Computer Engineering Thursday, April."— Presentation transcript:

1 Presented by Anas Mazady, Cameron Fulton, Nicholas Williams University of Connecticut Department of Electrical and Computer Engineering Thursday, April 28, 2011

2  Fast memory  Believed capable of replacing NAND flash  Capable of multi- bit storage ◦ Essential due to low packing density

3  RESET (0) by heating PCM above melting point and quenching  SET (1) by heating PCM above crystallization temperature and below melting temperature  READ by applying very small voltage pulse and measuring current draw (V=IR) ◦ Large current in crystalline phase, smaller current in amorphous phase

4 OXIDE TiN GST TiN V pulse Aluminum θ 5 nm 40 nm 30 nm 20 nm 100 nm 25 nm NOTE: Geometry is not drawn to scale 7 nm

5  Al ◦ High electrical conductivity ◦ Fabrication  SiO2 ◦ Poor thermal conductor ◦ Insulator  TiN ◦ Low thermal conductivity ◦ Adequate electrical conductivity ◦ Heater/heat sink

6  Ge 2 Sb 2 Te 5 (GST) ◦ High crystallization temperature ◦ Low melting point ◦ Adequate Data retention (~10 years at 80°C-90°C)

7  CMOS compatible fabrication techniques  Minimal thermal crosstalk (65 nm nodes)  Multi-bit storage possible

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9  0° to 90°  Large active region  smaller active region  High peak RESET current  lower current ◦ 26% reduction  High peak temperature  lower peak temperature  Larger GST area at 90° ◦ Heat diffuses over larger area ◦ Oxide confines heat

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13  4 nm to 20 nm  Constant theta angle  Constant 1.0 ns voltage pulse  Increase in active region size ◦ Must amorphize entire contact area  Reduction in voltage pulse ◦ Reduction in thermal resistance (oxide)  10.5 times more RESET current

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15 OXIDE TiN V pulse Aluminum 5 nm 40 nm 30 nm 20 nm 100 nm 25 nm NOTE: Geometry is not drawn to scale GST 7 nm

16  Lateral cross-section: 78.54 nm 2  GST thickness: 20 nm  Erase time: 1.0 ns  Programming voltage: 0.512 V  Read voltage: 150 mV  Low read current: 3.25 nA  High read current:1.04 µA  RESET current density: 133.7 MA/cm 2 ◦ Small contact area

17  Low (0) resistance = 46.2 MΩ  High (1) resistance = 144.2 kΩ  ~320 times less resistance  2-3 orders of magnitude  Large range ◦ Multi-bit storage

18 I PEAK = 3.25 nA R = 46.2 MΩ I PEAK = 1.04 µA R = 144.2 kΩ

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