1. Device Modeling and Simulation for VLSI Design Robert W. Dutton Stanford University Introduction-- TCAD Moore’s Law Scaling using TCAD : Intrinsic Devices Isolation (and other Parasitic) Effects Kinds of Modeling : Technology Design (Scaling and SPICE Files) Behavior Modeling ( ESD, RF & Substrate Coupling) Future Scaling Issues Transition to SyCaMore Project SyCa More

2. Circuit Device Process Technology Files Characterization Device Scaling Masks Interconnects Isolation Technology Computer-Aided Design=TCAD Extrinsic (and Layout) Intrinsic (active/passive devices)

3. EDA/TCAD Boundaries IC Layout Circuit Design & Verification Process Technology Device & Interconnect Design Extraction & ERC Behavior Models Behavior Models SPICE Models SPICE Models ECAD TCAD (EDA=Electronic Design Automation)

4. Transistor Scaling versus Year --Moore’s Law Gate Length (L) decreases with each technology generation… Density of gates doubles with each generation… Cost per transistor is reduced (~ 1/Density)... 0.4 0.3 0.2 0.1 0.0 | | | | | | | | 1995 2000 2005 2010 Gate Length (  m) Year L = = = Figure 1 Density of IC devices is doubling with each new generation Gordon Moore

5. Robert Dutton, Fairchild Fellow (Cal gEEk, circa-1967) Figure 2 Moore Dutton Grove

6. Moore’s Law and Scaling (what are the limits?) 0.4 0.3 0.2 0.1 0.0 | | | | | | | | 1995 2000 2005 2010 Gate Length (mm) Actual Oxide Atoms Wavelength at 193 nm Year Growing demands on Equipment side Growing challenges on Materials side =100 nm

7. IC Scaling Issues-- Front-End, Back-End & Substrate Intrinsic Devices: Junctions Contacts Dielectrics Substrate Engineering: Parasitics Packaging Back-End Simulation: Multi-layer materials Electro-Thermal } Need for New, Faster, Smaller Transistors…

8. TCAD-based Model Extraction (for SPICE) Simulations (and Measured Data) of I-V, C-V and transient behavior of Scaled Devices TCAD TCADTCAD Extraction of key SPICE parameters for “compact models” (i.e. MOS level 3, BSIM…) that are the: “technology file” used for circuit design.

9. Scaling Effects in MOS-- Quantum Mechanical Limits t ox =21A t ox =15A Log I g V g =0 MOS C-V and “gate current”:  Classical for >20Angstroms  Tunneling through gate-- Changes C-V Gate current BIG problem

10. Challenges on the Road Ahead 100 nm There are a range of physical, chemical and materials changes as IC technology moves into the sub 100 nm regime

11. Intrinsic Devices –Thin oxides –High-  dielectrics –Dopant Statistics –Alternatives (single electron, pillars, heterojunctions...) Extrinsic Devices –Trenches –Materials (metals, Low- ...) –Stress –Alternatives (free space, flip-chip, use of MEMS...) Future Scaling Issues Interconnect Technology Beyond Scaled- CMOS

12. Challenges at Atomic Scale (21st Century TCAD and MOS Scaling Limits) X ox S ilicon G ate Fundamental Changes: Atomic Scales New Materials Beyond Planar: Pillars 3D devices Nano-tubes... Honto ni chisaku natte ne! (or in English) Things are really getting small!

13. Synthesized Compact Models (SyCaMore) for Mixed Signal Design and Noise Analysis Robert Dutton Stanford University SyCa More Introduction Highlights & Project Status: –Algorithms and Model Generation –Test Circuits for Model Validation Plans Karti Mayaram Oregon State University &

14. What is the “substrate noise” problem? why is it important? (Atheros, ISSCC 2002, Paper 7.2) (Atheros, ISSCC 2002, Paper 5.4) Atheros Interest in single-chip integration issues Using state-of-the-art foundry technology Digital blocks represent most of the chip; they generate LOTS of switching noise The radio has very sensitive analog (RF) blocks that don’t like noise!!

15. Introduction-- RF/Mixed-Signal Noise Coupling VCO Phase Noise Noise spectra and coupling mechanisms depend on: –Circuit configurations--including layout & technology –Distributed device effects –Substrate behavior (including nonlinear effects) VCO Digital Block Substrate Transfer Function Digital Spectrum Frequency Noise couples via transistor bulk regions (g mb ) “Phase Noise” means that frequency of VCO is not exact (=system problem) Focus of the SyCaMore Project…

16. Oscillations and Voltage-Controlled Oscillators Feedback perspective A=a/(1-af), if af=1 we get infinite gain…or oscillations From EE 122 the phase-shift oscillator specifically uses series-parallel RC network to: Make |f|=1/|a| and Guarantee exact 0-degree phase shift Timing-based oscillations--this can be “ring oscillator” type or “charge-discharge” (of Capacitance) type

17. Example of Phase-Shift Oscillator (EE122) s (=j  )   Reminder about s-plane and poles moving into either LHP or RHP R1R1 R2R2 (-) (+) Inverting Gain amp. A v ~ -R 2 /R 1 Phase-shift Network  =0 and f o and attenuating by 1/A v

18. Basics of Timing-based Oscillators +Vcc Control Logic: S1 on (S2 off) Then S2 on (S1 off) S1 S2 C Timer Circuits: Schmitt Trigger 555 IC Many others... “x” is the portion of the total period for which the respective “I x ” is in control T 1 T 2 Time VV

19. Making a Voltage-Controlled (Ring) Oscillator Vdd Voltage Control (for Ix) Oscillator (“ring” type) Basic Point: Frequency of Oscillations directly proportional to the Current (Ix) which in turn is Controlled by a Voltage (see previous slide about “timing)

20. A word about PLLs (and role of VCO) -to-  VCO i ii  osc Key Objective of Phase-Locked Loop: Use the “phase comparator” block (X) to keep “red” VCO doing exactly what the incoming signal is doing. This can either: a) guarantee “clock synchronization” or b) “demodulate” FM signals (coming from “green”). o VCO i Input: voice signals… Output: FM-modulated signals… o

21. Test Structures-- Create Digital Noise Emulation (DNE) blocks and study the effect of digital noise on Phase-Locked Loops (PLLs) Power-Current profiles: Bluetooth (Atheros) Multiple Freq. Synth. (IBM) Digital 1 Digital 2 Analog 1 Digital 3 Digital 4 Analog 2 (Atheros, ISSCC 2002, Paper 7.2) Counter Multi- outputs substrate Simulation: Verify noise behavior Parameterize DNE’s Hardware Version of DNE: Test Chip Implementation: Programmed DNE (parameterized based on digital application domain) Suitable RF/Analog block(s) DNE2 DNE1 DNE3 A1 A4 A3 A2 Barcelona PLLs Digital Noise Emulators Programmed Digital Noise Emulator

22. Modeling Digital Noise -- how does “digital noise” get modeled, both in time and frequency domains Gate Level Simulator Total Current Waveform FFT Analysis Noise Spectrum inputs Power Information (->Current Spikes) | | | | | | | 0 0.5 1.0 1.5 2.0 2.5 3.0 Freq. (GHz) Spectrum [dBmA] Aggregation of block-level currents, based on power estimates, provides parameters of current injection. Transform to frequency-domain give good measure of noise spectrum. time Total Current

23. Current Noise Models -- simulation and mathematical Objective: Create mathematical model for current noises on supply rails…. Basic concept I noise (t)=I d,sat 1 *(fitted curve for transition curve of switch) 2 1 : the quadratic model for simplification. 2 : Example Current noise in the supply of an inverter with t rise =t fall =400ps Red : Mathematical model Blue : SPICE simulation What happens when a CMOS gate switches? Current Pulse on Vdd

24. Behavior simulation-- PLL with digital noise (flow chart of models, tools and key results) Mathematical current noise model Voltage noise model PLL simulation with noise model Output spectrum using MatLab Taking derivative (modeling di/dt noise) Adding to VCO input (most sensitive block in PLL) Substrate Network Noise Injection (lumped model) Circuitry VCO Idd Current Gnd Current Noise Model: Frequency of the inverter switching, 17MHz PLL: Reference frequency : 150MHz Center Frequency : 4.5GHz Sampling time : 100ps Results: Even and Odd harmonics of 17MHz observable with different amplitudes. Here’s simulations of PLL frequency response based on substrate noise coupling

25. Modeling Distributed Substrate Effects-- coupled simulation (including automated extraction of models) Plug-and-Play with Device Simulators: New materials New classes of devices and physical coupling effects Automated Extraction: Maintain physical mapping and technology dependencies Allows parameterization based on layout details SPICE Circuit Simulation: Analysis stage Solution vector Circuit matrix & RHS Analytical devices Compact Models Numerical devices Device Simulator(s) CO-DEvice-Circuit Sim. 11 22 V dd V OUT R L numerical (2D) substrate model 22 11

26. A Simple Example-- CODECS Simulations (two-tone results: complete device and resistor-lumped model) 11 22 V dd V OUT R L 22 11 V dd V OUT R L R SUB one-lump R Using two frequencies  1 (gate) and  2 (substrate) what are the observed “tones” at V OUT ? Additional tones mean that there are nonlinear (distortion effects) Differences between complete 2D device level and lumped model means distributed effects are important

27. Numerical model for substrate One-lump resistive model for substrate Simulation Results-- MOSFET Substrate Noise

28. 1KHz 2KHz 1MHz 2MHz Input Signal Substrate Signal 3MHz Frequency Domain Spectrum -- (substantial differences between full numerical and lumped substrates)

29. Modeling of Substrate Parasitics-- a more detailed study of topological effects Rsub from numerical simulation of the lateral portion of substrate Numerical Model Two Alternative Models For Substrate Resistor S G DB Rsub S G D B S G D B

30. Two-tone CODECS Analysis -- First Model D G S B 5V Spectrum of Next... S G D B Rsub distributed lumping

31. Spectre time domain simulations and H&L* analysis for uncorrelated substrate noise injection show jitter peaks at: –n  0 (for asymmetric) –5 n  0 (for symmetric) Oscillator Jitter-- Simulations and Analysis (comparisons of symmetric versus asymmetric noise injection) *H&L--Hajimiri and Lee, The Design of Low Noise Oscillators, Kluwer Academic Press, 1999  

32. Model Generation-- Synthesized Compact Models (SCMs) for the Substrate Effects Digital Source Nodes Coarse Mesh Analysis: Provides automated element mapping Includes aggregation of contact effects Analog Sensing Node L mask Parameterized Netlist of Components ….. D_trap 4 1 trap_model C1 1 4 scale_fact.1-X-F/cm^2 C2 4 2 scale_fact.2-X-F/cm^2 R_sub1 4 2 scale_fact.3-X-Ohms R_sub2 4 5 scale_fact.4-X-Ohms.model trap_model D (Is=# TT=# …) Parameterized Netlist of Components ….. D_trap 4 1 trap_model C1 1 4 scale_fact.1-X-F/cm^2 C2 4 2 scale_fact.2-X-F/cm^2 R_sub1 4 2 scale_fact.3-X-Ohms R_sub2 4 5 scale_fact.4-X-Ohms.model trap_model D (Is=# TT=# …) Parameterization of SCMs: Geometry based on Layout (which can in turn be driven by synthesis) Quantified number of lumps (based on 3D TCAD simulations) Characteristics of Substrate (extracted from 3D TCAD) Parameterization of SCMs: Geometry based on Layout (which can in turn be driven by synthesis) Quantified number of lumps (based on 3D TCAD simulations) Characteristics of Substrate (extracted from 3D TCAD) Lumped (SCM) Network: Physical-based topography; number of lumps frequency dependent Layout dimensions used to scale resistor; provides bi-directional link

33. Time to Summarize… Simulations and (TCAD) Modeling are useful for Scaling ICs-- Moore’s Law and Beyond: –Basic Transistor behavior (including technology scaling) –Extracting SPICE models –Understanding Parasitic Effects Substrate Noise Coupling is Key Challenge for future System-on- Chip (SoC) Integration: –Analog blocks are very sensitive (especially RF components) –Modeling of substrate coupling involves: TCAD-, SPICE- and Behavior-Level representations Thanks REUs!! –Justin –Jason –Jiambo –Qi

34. Where I’ll be Aug. 18-23, 2002 Dinner! We’re Too little!