1. Current (recycler) timing/trigger system appears to be sufficient for TeV BPMs - add injection event to beam sync - TSG FPGAs nearly full, but dropping MDAT decoder and 2 of 6 gates frees ~30% space - could run TSGs at 7.5MHz (instead of 53) - IP Digital I/O board can drive BLM ext dev bus and calibration

2. Tclk 53 MHz MVME2400 Echotek Clk Gen PMC UCD IP CarrierI/O Fanout IP Digital I/O IP UCD Cal ctrl/ BLM ext dev bus Beam Sync Ext Trig 53 MHz Gate IP TSG IP TSG A/D clocks Tclk Existing (recycler) timing system

3. Need to re-layout I/O fanout board to include latest revisions - suggested additions/changes modify number of clock inputs and gate outputs A/D clock generator? 53 MHz repeater FPGA to incorporate functions currently on IP carrier (TSGs, Tclk UCD, Digital I/O, VME interface) Tclk, beam sync simulator

4. I/O FanoutIP Carrier UCD Digital I/O TSG Option 1 Re-layout I/O Fanout board to current revision (no changes) [5 weeks]

5. Option 2 Re-layout I/O Fanout board with on-board or mezzanine FPGA [6-7 weeks] FPGA I/O Fanout

6. Use existing IP version until firmware is ported to new FPGA FPGA IP Carrier UCD Digital I/O TSG Fanout

7. BPM Cal Filter Echotek Filters Echotek BPM Cal Calibration select (optional filter select) RF Relay RF Relays

8. Filters Cal AA BB Calibration signal applied to any one of four BPM ports can be monitored on other three ports.

9. Calibration Board [4-5 weeks] MAX4820 RF relays Filters

10. CPUTiming Digital Receivers Calibration Splitters (BLM) Echotek Clock Gen PMC UCD

11. CPUTiming Digital Receivers Calibration (BLM) PMC UCD (Clock generator incorporated in Timing board)