1. Statistical Transistor-Level Methodology for CMOS Circuit Analysis and Optimization Zuying Luo and Farid N. Najm

2. Motivations With IC technology scaling into nanometer regime, leakage power increases (~3X-5X per generation) and is becoming an important measure in IC design Nanometer technology exhibits wide process variations This sets hard obstacles for power reduction subjected to the goal performance IC manufacturers need more advanced power-reducing CAD tools which must consider process variations. Transistor-level optimization algorithms can cut down more power consumption than their gate-level counterparts Finer granularity Our research is to develop an efficient transistor-level optimization tool that can handle process variations in the nanometer regime.

3. A Three-Fold Approach Transistor-level simulator: Includes delay, active power and leakage power simulators Deterministic transistor-level power optimization engine Statistical transistor-level power optimization engine Deals with process variations in nanometer technology

4. Transistor-Level Simulator Delay simulator: 3 orders of magnitude faster than HSPICE with 2-7% loss in accuracy alpha-power law is adopted for delay analysis Deals with heterogeneous gates Active power simulator: Based on analytical model that are accurate and efficient for active power calculation. Leakage power simulator: Based on look-up tables

5. Deterministic Transistor-Level Optimization Engine We propose a deterministic transistor-level optimization engine with several improvements over prior work We can simultaneously tune width, V th and length to optimize circuits. Reduces leakage power by 22.58% (average) over gate-level counterpart Circuit Netlist of smallest width, high-V T0 and standard length Gate-space optimization for performance goal with least power increase Transistor-space optimization for maximum power saving with performance constraint Optimal circuit of sized width dual-V T0 and dual-length Transistor-level delay&power simulator input output

6. Statistical Transistor-Level Optimization Engine The development of the statistical engine is in progress Among all kinds of process variations, we will study within-die channel length variations Key for delay and leakage power calculations We will transform delay, slack, leakage power, active power and sensitivity from deterministic terms to statistical terms Based on the statistical formulation, we can study statistical transistor-level optimization methods