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Control Unit : Hardwired vs. Microprogrammed Approach

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Presentation on theme: "Control Unit : Hardwired vs. Microprogrammed Approach"— Presentation transcript:

1 Control Unit : Hardwired vs. Microprogrammed Approach

2 Two Major Blocks in a CPU
Datapath Adders, multipliers, dividers Shifters, Registers Anything that changes or stores data Control Unit Controls the data How data is stored? Where is it stored? When should data be available?

3 Control Unit Correct sequencing of control signals
Much like human brain controlling various parts of body Sequence and timing is the key Any aberration will result in wrong operation

4 A Simplified Control Unit
Fetch Fetch Unit Decode Decode Unit Execute Execution Unit Write Back Write Back Unit

5 A Possible Implementation
2 to 4 Decoder Mod-3 Counter CLK

6 Timing Diagram CLK Fetch Decode Execute Write Back

7 Let’s Sample The Signals
1 1 1 1

8 Another Way to Generate Signals

9 Hardwired vs Microprogrammed
Use gates to generate signals Squeeze out the juice for performance Different logic styles possible Microprogrammed Store the control signals in the sequence Just read from the memory every clock cycle

10 A Model Computer (Richard Eckert, SIGCSE Bulletin, Vol. 20, No
A Model Computer (Richard Eckert, SIGCSE Bulletin, Vol. 20, No. 3, September 1988) IP 8 12 LA Accumulator PC LP EA EP 12 12 ALU S 12 LM MAR A EU 8 RAM R 12 12 W LB Register B 12 12 LI LD IR MDR EI ED 4 Control Bus

11 More Details L = Load E = Copy to bus A,S = Add and Subtract
Sign bit to control unit IP = Increment PC ACC ALU B PC MAR MDR RAM IR Control Bus R W LM IP LP EP LD ED LA EA S A EU LB LI EI

12 Active Controls Mnemonic Opcode Action Register Transfers LDA 1
Load Accumulator               1 A←(Mem) 1. MAR ←IR 2. MDR ←M(MAR) 3. A ←MDR EI,LM R ED,LA STA Store Accumulator 2 (Mem) ←A 2.MDR ←A 3. M(MAR) ← MDR EA,LD W ADD 3 A ←A+B 1. A←ALU(Add) A,EU,LA SUB 4 A ←A-B 1. A←ALU(Sub) S,EU,LA MBA 5 B ←A 1. B←A EA,LB JMP 6 PC ←Mem 1. PC←IR EI,LP JN 7 If –ve flag is set 1. PC←IR if NF is set NF : EI,LP HLT 8-15 Stop Clock “Fetch” IR ←Next Instruction 1. MAR ←PC 3. IR ← MDR EP,LM ED,LI,IP

13 Hardwired Unit IR Ring Counter Opcode T5 T1 Decoder Control Matrix
CLK IR Ring Counter Opcode T5 T1 LDA Decoder Control Matrix STA ADD SUB MBA JMP JN Halt NF Control Signals

14 Table with Sequencing IP = T2; R=T1+T4*LDA; LI=T2;
LP EP LM R W LD ED LI EI LA EA A S EU LB Fetch T2 T0 T1 LDA T3 T4 T5 STA MBA ADD SUB JMP JN T3*F IP = T2; R=T1+T4*LDA; LI=T2; LP = T3*JMP+T3*JN*NF; W=T5* STA; A = T3*ADD; EP = T0; LD = T4*STA; S = T3*SUB; LM = T0+T3*LDA+T3*STA ED=T2+T5*LDA; …..

15 Control Matrix Implement using discrete gates Usually done using PLAs
Large control matrices are implemented hierarchically For speed A well known process and design flows are widespread

16 An Alternate Implementation
MAP 4-bit opcode Starting Address Generator CD & 1* + IR NF 01 00 CLK uPC Map CD Meaning 1 * From IR Unconditional Branch within Microprogram NF=0 => Increment NF=1 => Conditional Branch +1 32 x 24 Control Store Control ROM Jump Address Microinstruction Register HLT Control

17 Control Store Control Word uInstruction Address Instruction Op-Code
Control Signals CD MAP HLT Addr. Of Next Fetch 00 01 02 1 XX LDA 03 04 05 STA 2 06 07 08 ADD 3 09 SUB 4 0A MBA 5 0B JMP 6 0C JN 7 0D 0F 0E Expansion 8-E 10-1E HLT F 1F The Add and Sub microroutines are different from what is there in the Eckert’s website Control Word

18 Example 1 – MBA followed by ADD
IP LP EP LM R W LD ED LI EI LA EA A S EU LB Fetch 00 01 02 1 XX LDA 03 04 05 STA 2 06 07 08 ADD 3 09 SUB 4 0A MBA 5 0B JMP 6 0C JN 7 0D 0F 0E Expansion 8-E 10-1E HLT F 1F 09 0B

19 Sequence for MBA,ADD 1. MAR ←PC 2. MDR ←M(MAR) 3. IR ← MDR B←A
MOV B,A 1. MAR ←PC 2. MDR ←M(MAR) 3. IR ← MDR B←A A←ALU(Add) ADD

20 Example 2 – JN with Flag Set
IP LP EP LM R W LD ED LI EI LA EA A S EU LB Example 2 – JN with Flag Set CD Fetch 00 01 02 1 XX LDA 03 04 05 STA 2 06 07 08 ADD 3 09 SUB 4 0A MBA 5 0B JMP 6 0C JN 7 0D 0F 0E Expansion 8-E 10-1E HLT F 1F 0D If negative FLAG is set, jump to a new location by skipping to uInstruction at 0F

21 Example 3 – JN with Flag Not Set
IP LP EP LM R W LD ED LI EI LA EA A S EU LB Example 3 – JN with Flag Not Set CD CD Fetch 00 01 02 1 XX LDA 03 04 05 STA 2 06 07 08 ADD 3 09 SUB 4 0A MBA 5 0B JMP 6 0C JN 7 0D 0F 0E Expansion 8-E 10-1E HLT F 1F 0D

22 Let’s Review the Microprogramming Model
Store the microprogram in control store Fetch the instruction Get the set of control signals from the control word Move the microinstruction address Lather, Rinse, Repeat

23 What is Microcode? Michael Slater's "Microprocessor Based Design" (pg.42):   Microcode tells the processor every detailed step required to execute each machine language instruction. Microcode is thus at an even more detailed level than machine language, and in fact defines the machine language. In a standard microprocessor, the microcode is stored in a ROM or a programmable logic array (PLA) that is part of the microprocessor chip and cannot be modified by the user.'

24 Thought Experiment Why is the design a little clumsy?
What can we do about it?

25 Reason for Clumsiness JN – Conditional Flag check
Without any condition check, the whole process is very smooth Solution – Avoid all conditional checks

26 Real Life A little American Football Story Theory vs. Practice
In theory, there is no difference between theory and practice In practice, theory and practice are two different things altogether Live with condition checks Keep designs as clean as possible

27 A General Approach Starting and Branch Address Generator
External Inputs IR Conditional Codes uPC Control Store Control Word

28 Format of Microinstructions
Pick yours Your choice is as best as your neighbor’s What we did : One bit position per control signal Order of the bits ? Don’t matter Can result in long microinstructions Not the number of microinstructions, but the width

29 A Note About Density Observe that only a few bits are set to 1
Poor usage of bit space This scheme is called Horizontal Microprogram Alternate Version : Encode the bits Vertical Microprogram

30 Vertical Microprogram
Encode the bits by grouping similar elements together General Idea : Group similar resources together There can be only one source or destination register Some operations are mutually exclusive Read vs Write of memory

31 Design Issues Encoding reduces the bit-space
But requires decoders Cost of decoder vs bit-space Usually decoder cost is very low

32 Another Idea Group concuurently active signals
Every meaningful combination gets a code Complex decoder to interpret every code

33 Vertical vs Horizontal
Faster More area More common currently Cheap transistors Vertical Slower More microinstructions

34 Microsequencing Other ways to save on hardware
Every instruction had its own microprogram sequence Also, instructions have several addressing modes Only the first few microinstructions differ Can we share microcode?

35 A Powerful Technique in Sharing
Bit-ORing Example Two instructions share some microcode Eventually, must branch The default branch (one instruction’s) is X0 The other branch is stored at X1 Change the least significant bit(s?) to get a new address Compare that with : Having two conditional branches Store two fields, one for each branch Both very unclean

36 Thought Experiment : What if we provided explicit branch instead of storing next field in our microprogram? Typical instruction set will need a lot of branches Lot of time will be wasted on branching

37 A Pat on Our Back We provided explicit field for address Caution :
Branch location is now data It is already saved Caution : Microinstruction can get very wide Solution : There is no free lunch.

38 Can we pipeline microfetch?
A neat idea : Why wait till the current micro-op is over? Branch field gives next operation Get the next op Caveat : External inputs and status flags may change the order What about interrupts? They are going to follow you everywhere Should have a mechanism that can invalidate microcode prefetch Similar to pipeline flush for instructions Commonly used

39 Historical Perspectives
Hardwired Logic Popular before 60’s Only way people did it Popular now Speed Benefits Microprogram Popular in 70’s Memory was slower than CPU No on-chip cache Best way is to store the microcode Now – Depends on who you ask? Shades of gray : Extremes of spectrum are harder to find nowadays

40 Tools for Design Hardwired Microcoding Any state machine optimizer
Assigning states, minimizing tranisitions, races, hazards,…….. Microcoding Small ones can be in binary Large ones – Use microassembler Very useful debug tool Can use microassembler simultaneously with actual hardware development

41 Hardwired vs Microcoding
Hardwired units are faster and smaller Emulation is easy with microcoding Hardwired design is complex if large Bugs in hardwired design cannot be fixed in field Hardwired control is not suited for loops Looping with microcode can be made as fast

42 Hardwired vs Microcode vs RISC
Simpler instruction set Hardwired Implementation RISC instructions are like microcodes Instructions come from I-Cache instead of Control Store Difference : Contents are not fixed Advantage : Only load what you want on the I-Cache Keeps size smaller as compared to Control Stores

43 Microprogram vs Software
Imagine Floating Point Division Solution 1 : Write in software Long process Error prone Many fetches repeatedly from memory for the given sequence of operations Solution 2 : Microcode Long process too – but designer’s not programmers Relatively error free – more thorough design Requires many cycles but fetched and used locally

44 Emulation A very common use of microcoding IBM System/360 Secret :
32 bit architecture 16-bit registers Secret : Most implementations were 8-bit Keep cost low Heavy microcoding Programmers oblivious In 1992, International Meta Systems (IMS) announced the 3250 Designed to emulate the x86, 68K, and 6502 architectures Uses customizable microcode, among other techniques Went bust, never released

45 Another Interesting Note
Writable Control Store What if you, a programmer, can write your own control store? Not a mad scientist thought Implemented in VAX 8800 PDP-11/60 IBM System/370

46 Current Trends Microcode Update Linux Utility - microcode_ctl
Companion to IA32 microcode driver It decodes and sends new microcode to the kernel driver to be uploaded to Intel IA32 processors Update is volatile – lost on reboots Microcode updates are also rolled into BIOS updates typically Ready even before an OS is loaded

47 Intel Said….. The Pentium(R) Pro processor and Pentium(R) II processor may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Many times, the effects of the errata can be avoided by implementing hardware or software work-arounds, which are documented in the Pentium Pro Processor Specification Update and the Pentium II Processor Specification Update. Pentium Pro and Pentium II processors include a feature called "reprogrammable microcode", which allows certain types of errata to be worked around via microcode updates. The microcode updates reside in the system BIOS and are loaded into the processor by the system BIOS during the Power-On Self Test, or POST.

48 Current Trends Hyperthreading in P4 Microcoding in P4
A second logical CPU Complete state of the system in both CPUs Microcoding in P4 Two pointers control flow independently Both processors share the ROM entries Access is alternated between the CPUs

49 Thank You


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