1. 1 Jyväskylä contribution to EMCal / PHOS trigger

2. 2

3. 3 Hardware EMCal TRU components are almost all bought Epson/Toycom EG-2121 LVDS clock chip with 125 MHz frequency remained unbought –It is not needed in the board actually, it was for scraped functionality, but retained for possible use in FPGA

4. 4 Hardware Prices for producing PCB are aquired from Finland and few other companies –Avicapinor cheapest so far PCB assembly in Finland is reasonable in price –6500 CHf total for 4 units (goes down a lot for bigger orders) One of costs for tooling is about 1/3 of the quoted price for PCB production and assembly

5. 5 Hardware budget Price for test boards is ~ 9600 CHf for one For full production price goes below estimated 5 000 CHf for one board This is because of starting costs for PCB production and assembly and the minimum purchase sizes for certain components.

6. 6 Hardware budget Spent money –Design: SFr. 7,316.33 –4 unit production purchases: SFr. 9,830.00 –10 unit production purchases: SFr. 638.00 –full production purchases: SFr. 2,588.19 –total: SFr. 20,372.52 To be spent –material for 4 units: SFr. 1022.87 for 10 units: check SFr. 350 for full production: SFr. 3,968.11 capacitors & resistors: SFr. 2,886.79 –pcb production: SFr. 4,240 –pcb assembly: SFr. 6,550 –total: SFr. 19,017.77 Unit price: SFr. 9600 +6 production estimate total SFr. 24,500 unit price SFr. 4,075 with using parts bought for proto production real unit price ~SFr. 6,300 IF no changes in design!

7. 7 FPGA coding Here shall be some contribution from us –Development code for TRU v2 –Bigger V5 chip provides possibilities to be researched multiple trigger schemes? π 0 trigger isolation trigger

8. 8 Trigger scheme evaluations 1/2 We are starting to evaluate different energy levels for triggering at TRU –Event generation with ALIroot (Rafael Diaz is our expert on this) Real good events + beam gas (+ noise) –Comparison of the trigger energy levels with ratios of wrongly triggered events and missed events

9. 9 Trigger scheme evaluations 2/2 Other schemes to be developed and tested –isolation –  0 recombination trigger

10. 10 Sliding window trigger

11. 11 Sliding window trigger levels single level or multiple level? How to select levels?

12. 12 Simulated PHOS event with Pythia 6 QCD jet-jet in p+p 14 TeV Alice Geant3 Full simulation with TPC, ITS, PHOS, EMCAL switch on. Not material in front of PHOS. Aliroot version : v4-06-Rev-04 will these trigger or be lost in noise?

13. 13 Trigger level selection Last slide illustrated some of the difficulties in selecting the trigger levels. Good simulations and rigorous analysis is needed for selecting the levels, so we wont be triggered on beam gas nor electronic noise. But we don’t want to loose good events by too high trigger level...

14. 14 EMCal supermodule trigger regions 1 FEE card readout region (8x1 modules) 24 modules (48 towers) 12 modules (24 towers) 12 FEE cards are used to read out 8x12 modules region -> output to 1 TRU card 3x12 FEE cards read out whole super module -> 3 TRU cards

15. 15 EMCal FEE readout region 1 module (2 towers) 8 modules (16 towers) sum 1 (4 towers) sum 2 one FEE board supplies 8 analog sums, each representing one module 12 FEE boards supply 1 TRU board with 8x12 = 96 analog sums, which is 1/3 of super module

16. 16 Hardware testing for EMCal TRU We need to design the test scheme (or just copy it from TRU v1 tests) Needed devices –Logic analyzer –signal generator –? Place for testing JYFL and/or CERN? –probably both?