1. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 1 SiECAL DAQ Taikan Suehara (Kyushu University, Japan)

2. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 2 SiECAL Block diagram CCC SKIROC2 Si DIFs GDCC/LDA PC Spill External clock 16 x 1-8 chips/DIF, 64 ch/chip Flexi connector HDMI (Command/Data) Raw Ethernet (Data, Command) Pyrame2/Calicoes2 HDMI (Fast command, clock, (busy) )

3. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 3 (old) Slab + DIF CCC LDA

4. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 4 Before configuration CCC SKIROC2 Si DIFs GDCC/LDA PC Spill External clock Clock (Dedicated line), Start, Stop (Fast command) Spill ignored

5. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 5Configuration CCC SKIROC2 Si DIFs GDCC/LDA PC Configuration / reply Slow control etc. No configuration

6. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 6 After configuration: command flow CCC SKIROC2 Si DIFs GDCC/LDA PC Spill External clock Clock (Dedicated line), Start, Stop (Fast command) Clock, Start, Stop Rising and Falling edge of spill converted to fast commands in CCC No command related to start/stop

7. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 7 After configuration: data flow CCC SKIROC2 Si DIFs GDCC/LDA PC Data Data packet (raw Ethernet) Arrange and add DIF header Arrange and add LDA header Passive recepient

8. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 8 CCC: UK origin LDA: UK origin, raw ethernet –being replaced to GDCC in LLR –“compatible” design but fewer packet drop DIF: Communicate with compatible commands to UK DAQ –8b/10b encoding, oscillating BUSY Technology overview: hardware

9. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 9 Pyrame: a modular framework for testbench based on python –New version released, well documented –http://llr.in2p3.fr/sites/pyrame/http://llr.in2p3.fr/sites/pyrame/ SiECAL module is coded on CALICOES on pyrame Technology overview: software

10. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 10 CALICOES (pyrame) has a socket output –I attached a EUDAQ module via this for CERN TB Configuration can be done in the framework –Send a message to configure may be possible but not done in CERN TB pyrame has event-building feature, but currently not used for combined DAQ –Since we built events inside EUDAQ CALICOES (old) and EUDAQ in CERN TB last year

11. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 11 Timing chart spill start/stop CCC  LDA  DIF  ROC acquisition 500 usec data ROC  DIF  LDA  PC

12. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 12

13. Taikan Suehara, LCWS @ Belgrade, 9 Oct. 2014 page 13 Common master clock frequency –To assure simultaneous BX counting Common BX clock frequency BUSY treatment  Common CCC? or just clock synchronization? High level DAQ software (EUDAQ?) –Run control, event building, run number, monitoring,… Common data format (LCIO class) Partial or optional sharing of firmware and software etc. Things to discuss (shown in kickoff)