1. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 1 Status of SiW-ECAL development for ILD Taikan Suehara (Kyushu University) on behalf of ILD SiW-ECAL development group

2. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 2 ILD Silicon-ECAL development

3. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 3 ILD Silicon-ECAL development France LLR, LAL, LPNHE, LPSC Japan Kyushu, Tokyo

4. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 4 Silicon-ECAL: design

5. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 5 Physics & Technological prototype 16.5%(stochastic) 1-2% (constant) obtained with 1-45 GeV e - /e + at 2006/2008 BT Physics prototype: -2008 PFA proof with comparison to MC (Pandora etc.) electronics outside 1cm x 1cm pixels full 30 layers Technological prototype Full integrated electronics between Si/W layers SKIROC2 analog/digital ASICs Mainly for realization of electronics and mechanics to realistic detector

6. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 6 Progress in Si-ECAL development Mechanics PCB production (BGA/CIB) Gluing Assembly Cooling DAQ ASICsDIFs LDA/GDCCsCCC PCs Guard rings Doping Sensor design ASIC performance GDCC with UDP Software Adaptation to larger DAQ Overall size Layers Hybrid Optimization

7. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 7 Progress in Si-ECAL development Guard rings Doping Sensor design

8. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 8 Basic sensor study Two batches of Hamamatsu sensors C-V curve: saturation V differs

9. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 9 Laser study with guard rings 3x3 babychip 4x4 ongoing laser Nd:YAG laser (1064nm) focused to  20  m ~ 1.5 ns pulse width ~13 kW peak power 10,000 pulses measured 120V bias voltage on silicon DAQ by PHADC on CAMAC upper-left ch by power calibration

10. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 10 1 guard ring laser GR effect seen: esp on edge pixels

11. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 11 4 guard rings (separated) laser GR effect much smaller

12. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 12 Mesh pixels microscope Baby chips with meshed electrodes have been arrived. Being prepared for laser injection INSIDE pixels.

13. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 13 Progress in Si-ECAL development Mechanics PCB production (BGA/CIB) Gluing Assembly Cooling

14. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 14 FEV 8  9  10 (BGA package) FEV8 QFP SKIROC2 4 chips/board (256ch) used in 2012/13 BT 10 slabs exist FEV9 (LLR)16 BGA SKIROC2 Good flatness (< 0.5 mm) Some bugs fixed Cabling done(?) Electronics test will be done soon 4 FEV9 will be interconnected for long slabs FEV10 will be used for 2015 BT

15. Reminder FEV_COB 15 - Interface board with Chip On Board - Assures compact calorimeter - Not trivial specs Ultrathin : 9 layers with thickness of about 1.2mm Deviation of total planarity of about 0.5 mm (3mm is industrial standard) However it's now there in a first version - Design and routing OMEGA/LAL - Fabrication end of 2012 - Metrology at LAL - Chips mounted beginning of 2013 by CERN bonding lab - First tests in summer 2013 at LAL

16. Cooperation with EOS 16 - Korean company EOS has declared to be ready to produce the PCB -> Relaxed constraints on the thickness 1.2mm -> 1.5mm - Technical discussion ongoing via mail but production is imminent - Plans to assure entire PCB assembly in Korea - PCB production - ASIC bonding - Encapsulation

17. Current gluing status 9 sensors has been glued with the robot: used at 2012-13 beam tests The constraints on the PCB geometry have been identified: – Flatness – Parallelism of the edges – Uniform height of the ASIC soldered on the board The leakage currents measured before and after the gluing process are similar. 17 Improvements – Use of specific pumps for dry and clean vacuum – Careful cleaning of PCB – New positioning of the glue dots for the external pads, to avoid short-circuits.

18. Next steps We need to develop the software for automated positioning and alignment (almost completed) We plan to combine both gluing and positioning robots (already assembled) The robots will be moved and installed in the clean room (not yet) The goal is to glue 4 sensors on the same PCB (already done with 4 glass tiles on FEV9) 18

19. Both robots assembled 19

20. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 20 Assembly mechanics Interconnection of 4 FEVs Building on going of transport and handling tools for integration & tests ~2,56 T Optimization of fastening to Carbon HR Rails EUDET Carbon HR plate 13 mm with metallic inserts Mechanical structure of frames

21. CALICE Collaboration Meeting March 2014 Power dissipation : Final goal with power pulsing 1/100 s Barrel : (1.5m)  T = 2,2°C For ½ SLAB from barrel Wafers consumption : 0.205 W Front SLAB electronic : 0.3 W Ecal detector : 4.5 kW 0.205 W / surface 1.5 m x 0.18 m 0.3 W Front SLAB electronic Heat exchanger location End Cap : (2.5m)  T = 6°C Passive cooling : OK Cooling capacitites … support up to 10x bigger heat load (for details see backup)

22. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 22 Progress in Si-ECAL development DAQ ASICsDIFs LDA/GDCCsCCC PCs ASIC performance GDCC with UDP Software Adaptation to larger DAQ

23. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 23 ASIC tests w/ testboards SKIROC2 64ch readout/chip preamp + 2 shapers Autotrigger 15 cell analog memory 14 bit ADC SKIROC2 test board developed by OMEGA No detector, input holes Analog/digital tests Automated test software with Labview Some crosstalk found

24. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 24 Tests for BGA SKIROCs FEV9 test board in LLROMEGA test board for BGA Both analog/digital tests Being prepared in Kyushu Based on QFP test board Redesigned w/ BGA BGA socket equipped - or BGA soldered for comparison Possibility to connect to DIF as well as old FPGA Close contact with S. Callier of OMEGA Expected in June or July Equip one socket at one channel of FEV9 Digital test only

25. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 25 Crosstalk with FEV8/injection

26. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 26 Issues in SKIROC2/FEV8 Post triggering of BX+1, BX+2 at many channels –improved by decoupling capacitor but still exists Noisy channel – ~10%? (PCB routing?) External trigger not working TDC (maybe too noisy) Initial configuration sometimes fails –maybe problem on DAQ rather Some of them will be improved in FEV9/10

27. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 27 7 x DIFs HDMI CCC HDMI RJ45 & fiber connector VME connector USB connector Main part Mezzanine part (HDMI interface) VME6U, based on mainly commercial components Used from 2013 summer: many improvements done Data loss << 1% in previous BT, robustness shown Testing UDP bloc The GDCC card Will be used with 160 chips in the next beam test

28. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 28 Calicoes: the SiECAL DAQ software Acquisition chain Control commands XML transfer by sockets (python implementation) Low level part written in C (pyrame framework)

29. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 29 ASIC configuration tool Ruby + GTK

30. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 30 We should integrate on larger DAQ systems for combined testbeam etc. We plan to use EUDAQ (as a first trial) Also investigating Si/Sc combined DAQ for hybrid ECAL –Or anyone else using ROC chips –Or more (trackers?) into real ILD? Hopefully come first in this summer Efforts for larger DAQ

31. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 31 We received: –One Slab (FEV8 used in beamtests) –One DIF –One LDA, one CCC Technology has been basically transferred in my visit to LLR in last winter –including CALICOES We start to reproduce the same setup as LLR, then start to contribute to DAQ/test DAQ imported to Kyushu

32. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 32 Progress in Si-ECAL development Overall size Layers Hybrid Optimization

33. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 33 Optimization with PFA Optimization is not straightforward How do we constrain costs? How about multiple thicknesses? How is the physics affects? Study still ongoing

34. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 34 PCB thickness Seems smaller effect in PCB thickness < 3 mm Current Si/QFP has 3.1 mm thickness – can be reduced by thinner BGA Possibly COB with ~ 1.5 mm DBD: 1.2 mm maybe too optimistic

35. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 35 Optimization of “Hybrid” We will move to more strategic way...

36. Taikan Suehara, AWLC14@FNAL, 13 May 2014 page 36 We will finalize the optimization –Of sensors –Of geometries (with physics motivation) We will prepare for the next BT in 2015 –With FEV10/GDCC/software –With bigger scale of production We will prepare for the mass production –Automated test/assembly etc. –More consideration on mechanics We will widen the collaboration/cooperationSummary