1. 1 A Fast Algorithm for Power Grid Design Jaskirat Singh Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota

2. 2 Introduction Power supply network Power supply network Provides VDD and ground to time varying current sources (logic gates) Provides VDD and ground to time varying current sources (logic gates) VDD GND Power grid design issues Power grid design issues VDD, wire width, currents VDD, wire width, currents IR drop/ground bounce IR drop/ground bounce Signal integrity Signal integrity Gate delay Gate delay Electromigration Electromigration Mean failure time for wires Mean failure time for wires

3. 3 Introduction Power grid design problem Power grid design problem Given an estimate of loading currents and power pad positions Given an estimate of loading currents and power pad positions Select a set of wire widths and pitches for the multiple-layer network so that Select a set of wire widths and pitches for the multiple-layer network so that Wire area is efficiently utilized Wire area is efficiently utilized Nodes (branches) satisfy voltage drop (current density) constraints Nodes (branches) satisfy voltage drop (current density) constraints Additional objectives of congestion minimization/shielding Additional objectives of congestion minimization/shielding

4. 4 Introduction Power grid design methods Explicit circuit simulation based method Detect and fix method Accurate Design Usually slow Non-linear optimization based method KCL/KVL part of constraint set Approximations needed for efficiency May be inaccurate due to relaxations

5. 5 Motivation Notion of locality in power grid design Notion of locality in power grid design “Fast Flip-chip Power Grid Analysis via Locality and Grid Shell”, Eli Chiprout, ICCAD’04. “Fast Flip-chip Power Grid Analysis via Locality and Grid Shell”, Eli Chiprout, ICCAD’04. To construct local grids focus on details of local regions. Abstract far away regions of the grid. To construct local grids focus on details of local regions. Abstract far away regions of the grid.

6. 6 Locality Example 10 X 8 Grid 10 X 8 Grid Fix Violations Locally Abstract away far off grid regions Power Grid Abstraction Each branch 1 ohm Each branch 1 ohm Loaded with 1mA Loaded with 1mA Vspec = 0.9V Vspec = 0.9V VDD pads (1V ) VDD pads (1V )

7. 7 Locally Regular/Globally Irregular Globally regular grid Globally regular grid Over design of the grid Over design of the grid Globally irregular/locally regular grid Globally irregular/locally regular grid Efficient use of wire area Efficient use of wire area Reduced # of optimizable parameters Reduced # of optimizable parameters High MedLow High MedLow High MedLow

8. 8 Power Grid Design Procedure Recursive bipartitioning heuristic based on notion of locality Abstraction of grids in partitions Coarse grid representation initially Post processing step to maximize wire alignment Divide the chip area into partitions Design local grids in the partitions Macromodeling technique by M. Zhao et al, DAC’00 Iterative refinement of grid

9. 9 Recursive Bipartitioning Method Divide and conquer approach Divide and conquer approach Solve a local power grid design problem in each step Solve a local power grid design problem in each step 1 2 3 4 5 3 2 k 2 K+1 Vertical, horizontal partition wire Vertical, horizontal partition wire Active partitions Active partitions

10. 10 Recursive Bipartitioning Method Level-1 Partition Level-2 Partition Level-k Partition

11. 11 First level of partitioning Construct macromodels for the two partitions Construct macromodels for the two partitions Port Nodes

12. 12 First level of partitioning Stamp the macromodels in the global MNA system Stamp the macromodels in the global MNA system Solve each partition by hierarchical analysis Solve each partition by hierarchical analysis For violations in a partition, fix it locally For violations in a partition, fix it locally Speed up in circuit analysis step Speed up in circuit analysis step Use very thick wires for initial partition levels Use very thick wires for initial partition levels In subsequent partition levels refine the grid by reducing the wire width In subsequent partition levels refine the grid by reducing the wire width

13. 13 Second level of partitioning Rip up the grid in left partition Rip up the grid in left partition Add a horizontal partition wire Add a horizontal partition wire Leave the grid in the right partition intact, seen as an abstraction Leave the grid in the right partition intact, seen as an abstraction Construct a refined grid in the top-left and bot-left partitions by the Construct a refined grid in the top-left and bot-left partitions by the hierarchical design methodology hierarchical design methodology Use the power grid constructed at the first level Use the power grid constructed at the first level

14. 14 Second level of partitioning Requirements for power grid constructed in new active partitions Requirements for power grid constructed in new active partitions IR drop and EM constraints met in the active partitions IR drop and EM constraints met in the active partitions Maintain correctness of the power grid in the right partition Maintain correctness of the power grid in the right partition Solve new global system M X=b Solve new global system M X=b Compare old and new port voltages of the right partition Compare old and new port voltages of the right partition If Max( New_port_voltage – Old_port_voltage) > є (e.g., 1% VDD) If Max( New_port_voltage – Old_port_voltage) > є (e.g., 1% VDD)  Power grid in right partition is disturbed  Power grid in right partition is disturbed  Add more wires in the active partitions and repeat the design procedure  Add more wires in the active partitions and repeat the design procedure γ

15. 15 Make next partitions Decr width by γ Decr pitch by β Detect violations Recursive bipartitioning algorithm Solve by hierarchical analysis Make macro Make macro Decr width by γ Make next partitions Check neighbor port voltages Port voltage change > є ? Post processing to align wires Done Repeat

16. 16 Recursive bipartitioning algorithm A breakdown scenario A breakdown scenario Min pitch violation Min pitch violation Grid refinement doesn’t work Grid refinement doesn’t work Grids in neighboring partitions disturbed Grids in neighboring partitions disturbed Can’t be fixed by adding wires in active partitions Can’t be fixed by adding wires in active partitions Traverse to the inactive partitions and add more wires Traverse to the inactive partitions and add more wires Adversely affects the runtime of the procedure Adversely affects the runtime of the procedure Empirically a rare event if Empirically a rare event if γ is [ 0.65,1 ) Make_macromodels( ); Solve_grid( ); If(violations in one or both partitions) Decr wire pitch of violating partition; Check_neighbor_grids( ); If(port nodes of neighbor grids perturbed) Decr wire pitch of active partition; If (Pitch of the active partition < min_pitch) Min pitch violation; γ

17. 17 Post processing step At the end of design the wires might be misaligned due to different wire pitches in adjacent partitions At the end of design the wires might be misaligned due to different wire pitches in adjacent partitions Superimpose a uniform and continuous virtual grid Superimpose a uniform and continuous virtual grid Pitch of the virtual grid is chosen to be the minimum pitch of all partitions Pitch of the virtual grid is chosen to be the minimum pitch of all partitions Move the real power grid wires to the nearest vacant position on the virtual grid Move the real power grid wires to the nearest vacant position on the virtual grid Perform a complete simulation by hierarchical analysis after the wire movements Perform a complete simulation by hierarchical analysis after the wire movements Add more wires if required on the virtual grid place holders Add more wires if required on the virtual grid place holders

18. 18 Experimental Setup Input Input Floorplans with functional block current estimates Floorplans with functional block current estimates Power pad locations and number Power pad locations and number Grids constructed for power delivery to 2cm X 2cm chip Grids constructed for power delivery to 2cm X 2cm chip Vdd=1.2V, Vspec=1.08 V Vdd=1.2V, Vspec=1.08 V Sheet resistivity, current density, min pitch for 130nm tech Sheet resistivity, current density, min pitch for 130nm tech Flip-chip (FC)  400-600 power pads Flip-chip (FC)  400-600 power pads Wire-bond(WB)  200-300 pads located at the periphery Wire-bond(WB)  200-300 pads located at the periphery Initial wire width 60-100 µm, k=7 levels of partitioning Initial wire width 60-100 µm, k=7 levels of partitioning γ in (0.65,1], β in (0.5,1], є=15mv γ in (0.65,1], β in (0.5,1], є=15mv Output Output A non-uniform power grid that meets the IR drop and EM constraints A non-uniform power grid that meets the IR drop and EM constraints Wire width at the end of design is 2-6 µm Wire width at the end of design is 2-6 µm

19. 19 Experimental Results Ckt # of Blocks # of Nodes ( in millions) ( in millions) Wire Area Run Time (10 -2 cm 2 ) (10 -2 cm 2 ) (sec) (sec) FC FC WB WBFCWBFCWB pg-1171.561.638.128.52443661 pg-2171.191.227.838.16517787 pg-3121.261.387.217.54653839 pg-4161.051.216.887.38617842 pg-5201.221.347.048.06572805 pg-6241.141.197.227.86683935 pg-7201.641.708.5210.22431692 pg-8221.291.368.409.92452671 Power grids > 1M nodes designed in 7-12 mins for FC and 11-16 mins for WB Power grids > 1M nodes designed in 7-12 mins for FC and 11-16 mins for WB Wire bond designs are suboptimal due to absence of locality property Wire bond designs are suboptimal due to absence of locality property

20. 20 Experimental Results Proposed method compared with a previous work Proposed method compared with a previous work K. Wang and M. M Sadowska, “On-chip Power Supply Network Optimization using Multigrid-based Technique”, DAC’04 K. Wang and M. M Sadowska, “On-chip Power Supply Network Optimization using Multigrid-based Technique”, DAC’04 Multigrid method based on mapping from original space to a reduced space Multigrid method based on mapping from original space to a reduced space Original mesh Original mesh Reduced mesh Reduced mesh Optimization engine Optimization engine Multigrid Reduction Back mapping

21. 21 Experimental Results % Saving in power grid wire area 7%-12% reduction in wire area over the multigrid-based method

22. 22 Experimental Results Constraints in the multigrid-based method Constraints in the multigrid-based method All rows (columns) of wires are constrained to have the same width All rows (columns) of wires are constrained to have the same width Wastage of wiring resources Wastage of wiring resources Current Densities High Med Low High Med Low High Med Low

23. 23 Experimental Results Runtime comparison of the two power grid design methods Runtime is of the same order for the two methods

24. 24 Summary A novel and efficient power grid design procedure proposed A novel and efficient power grid design procedure proposed Use notion of locality in grid design Use notion of locality in grid design Accuracy is maintained by using circuit analysis step in the inner loop Accuracy is maintained by using circuit analysis step in the inner loop Circuit analysis is made efficient by the use of Circuit analysis is made efficient by the use of Grid abstractions Grid abstractions Coarse initial grid models followed by successive grid refinements Coarse initial grid models followed by successive grid refinements Considerably fast power grid design method with efficient wire area utilization Considerably fast power grid design method with efficient wire area utilization

25. 25 THANKS !!! THANKS !!!