1. RSC MAPLD 2005/130Hodson Robert F. Hodson 1, Kevin Somervill 1, John Williams 2, Neil Bergman 2, Rob Jones 3 1 NASA LaRC, 2 University of Queensland, 3 ASRC Aerospace An Architecture for Reconfigurable Computing in Space

2. RSC MAPLD 2005/130Hodson 2 RSC Goals & Objectives To develop the next generation high performance space- qualified computing system leveraging… –Field Programmable Gate Arrays FPGAs –Intellectual Property (IP) Soft cores, processors –COTS software architectures Multi-processor Specialized Meet Strategic Challenges –Reconfigurability –Modularity First step towards the next generation avionics suite

3. RSC MAPLD 2005/130Hodson 3 Why Reconfigurable Computing with Soft Cores & Custom Logic Source: R. Lysecky and F. Vahid, “A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning,” Design Automation and Test in Europe (DATE), March 2005 Soft cores readily available for rad-tolerant FPGAs Custom co-processors can improve performance on average by 5.8X Power consumption can also be reduced on average by 57% Reconfiguration allows many designs without hardware redesign – reducing cost Making this approach competitive with current space computing systems

4. RSC MAPLD 2005/130Hodson 4 Scalable Architecture Multiple interconnected general purpose processing nodes with optimized custom logic attached for special purpose processing.

5. RSC MAPLD 2005/130Hodson 5 Physical Concept Stacks of reconfigurable processing modules (RPMs) similar to a ruggedized version of a PC104+ stack. Modules, which make up a stack will be RPMs, Command Control Module (CCM), Network Module (NM), etc. Physical design will support launch loads, radiation shielding, and conduction cooling. STACKS Modules

6. RSC MAPLD 2005/130Hodson 6 Modular Technology Modules will be combined to build RSC systems Designs will be based on rugged small form factor modular stackable technology –Allows mixing and matching of appropriate modules to meet mission requirements Planned modules –Reconfigurable Processing Module (RPM) –Command/Control Module (CCM) –Network Module (NM) –Power Module (PM) Command Control Module (CCM) Reconfigurable Processing Module (RPM) Network Module (NM) Reconfigurable Processing Module (RPM) Reconfigurable Processing Module (RPM) Power Module (PM) BUS

7. RSC MAPLD 2005/130Hodson 7 Multiple Interconnected RSC Stacks

8. RSC MAPLD 2005/130Hodson 8 Software Architecture RSC plans to deliver a complete system with hardware, system software, development software, and a demonstration application. uCLinux MPI

9. RSC MAPLD 2005/130Hodson 9 Reconfigurable Processing Module SDRAM (512 MB) Config Memory Config Mgr NVR I/F NVRAM (FLASH or CRAM 32MB min) SDRAM I/F SLin SLout Actel FPGA Xilinx FPGA ( V4FX60) Bus SERDES (2.5 Gbps) Parallel IO Serial IO Switch NIC Data Cache PCI I/F PCI Bus 33MHz 32/64 Bits uB Custom Logic Instr Cache RPM Frame Buf

10. RSC MAPLD 2005/130Hodson 10 RPM Features Xilinx logic is triplicated and scrubbed –Custom cache design (MicroBlaze cache not used) Caches will be scrubbed SDRAM is SECDED protected and scrubbed. Rad-Hard NVRAM is an issue Compressed code image and configuration is stored in NVRAM. It is copied to SDRAM and decompressed after reset. –If the system has multiple MicroBlaze processors they each have separate memory space in the same physical memory. Custom logic can communicate via FSL or OPB PCI interface supports Master/Target/DMA

11. RSC MAPLD 2005/130Hodson 11 RSC Protocol Stack Transport Application/MPI Network datagrams Data Link and Physical packet message Internet Protocol UDP Buses Sockets Message Data PHdr IP Data PHdr IP NIC Data Receiving CPU or NM Message DMA Engine PCI Address and Size of Datagram Network Req IP Address and Size of Datagram Pull NIC INTR ACK Sending CPU

12. RSC MAPLD 2005/130Hodson 12 Communication Event Sequence PCI I/F IP2PCI Mapping SDRAM CPU Message Buffer Controller Req queue PCI I/F IP2PCI Mapping Controller Req queue SDRAM CPU Message Buffer Source RPM Destination RPM 1. Datagram is built in memory. 2. Message send request. Source NIC Destination NIC 3. IP address is translated to PCI address of destination. 4. PCI Address of message on source RPM sent to destination NIC. 5. Destination NIC pulls (DMAs) message into destination RPM’s memory. 6. Message received interrupt sent to CPU. 8. Destination NIC tells source NIC “message received.” 7. Message processed. 9. Interrupt to source CPU. Buffer can now be released. PCI Bus

13. RSC MAPLD 2005/130Hodson 13 Command & Control Module PCI Master/TargetPCI Arbiter Reset Power Mgmt 1553 Command I/F System Reset Power Good Configuration and Code Selects uController PCI Backend I/F Hub MemoryNVRAM Test port IO Controller Memory Controller Discrete IO PCI The Command and Control Module (CCM) provides the primary command interface to the system. If also controls the system bus initialization and boot process. CCM

14. RSC MAPLD 2005/130Hodson 14 Network Module Design Control Routing Lookup Control Routing Lookup DMA SERDES To Other Link InterfacesFrom Link Interfaces From Link Interfaces Link I/F PCI I/F Actel AX2000 To/from other stacks Additional Link I/Fs SERDES Network Module (NM) provides an interface to other RSC stacks. It buffers and routes IP packets based on routing information loaded during system initialization. Serialized links provide a high-bandwidth interconnect to other systems.

15. RSC MAPLD 2005/130Hodson 15 RSC Robotic Demonstrator Demonstrate reconfigurable technology on a challenging real-time control and processing application Tele-operated robot with multiple sensors –Stereo camera –Omni camera –IR camera –X-Ray florescence sensor –Several others

16. RSC MAPLD 2005/130Hodson 16 RSC Team Core Team Members –NASA Langley Research Center (Lead) –NASA Goddard Space Flight Center –The University of Queensland –ARSC Aerospace –Jefferson Lab (DoE) –Starbridge Systems –Department of Defense Affiliate Members –Air Force Research Laboratory –SEAKR Engineering –Imagination Engines