Micro-Controller 8051 Overview

Micro-Controller 8051 Overview

MicroProcessor Part II
MCS-51 Family Overview 80C51 Family Products Pin Compatible MicroProcessor Part II

MCS-51 Family Overview Architectural Structure of the 8051 Family FREQUENCY REFERENCE COUNTERS OSCILLATOR & TIMMING ROM / EPROM RAM TWO 16-BIT TIMER/EVENT COUNTERS CPU 64K BYTE BUS EXPANSION CONTROL PROGRAMM- ABLE I/O PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFTER Int INTERRUPTS Ext INTERRUPTS CONTROL PARALLEL PORTS ADDRESS DATA BUS I/O PINS SERIAL IN / SERIAL OUT MicroProcessor Part II

Internal Block Description MicroProcessor Part II
MCS-51 Family Overview Internal Block Description MicroProcessor Part II

MCS-51 Family Overview Main Features of 8051 UART : Universal Asynchronous Receiver/Transmitter MicroProcessor Part II

External Pin Description MicroProcessor Part II
MCS-51 Family Overview External Pin Description P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Address/Data Bus Bidirection I/O Port /PSEN ALE /EA /RST P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Bidirection I/O Port RD WR T1 T0 INT1 INT0 TXD RXD P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A15 A14 A13 A12 A11 A10 A9 A8 Bidirection I/O Port Address Bus Bidirection I/O Port MicroProcessor Part II

Executing From External Program Memory MicroProcessor Part II
MCS-51 Family Overview Executing From External Program Memory Timing CLK ALE /PSEN PORT2 PORT0 LATCH Bus Cycle MicroProcessor Part II

MCS-51 Family Overview Executing From External Program Memory Structure 8 5 1 EPROM DATA(AD7~AD0) P1 P0 /EA ALE LATCH A7~A0 Lower Addr. Addr Upper Addr. (A15~A8) P3 P2 /OE /PSEN MicroProcessor Part II

MCS-51 Family Overview Executing From External Program Memory Example 8 5 1 EPROM P3 P2 P1 P0 /EA ALE LATCH Addr /OE /PSEN 87h Read Address 0421h (87h) Upper Address : 04h Lower Address : 21h EA : High : Internal Data Memory EA : Low : External Data Memory P0 : Address / Data I/O Port P2 : Address Bus MicroProcessor Part II

Executing From External Data Memory MicroProcessor Part II
MCS-51 Family Overview Executing From External Data Memory Structure 8 5 1 RAM P1 P0 LATCH ALE Addr ( 0~64KB) 216 = 64KB RD WR P3 P2 /CE DECODING WR /OE MicroProcessor Part II

MCS-51 Family Overview Executing From External Data Memory Timing - Read　 CLK ALE PSEN ／ＲＤ PORT2 PORT0 LATCH Bus Cycle MicroProcessor Part II

MCS-51 Family Overview Executing From External Data Memory Timing - Write　 CLK ALE PSEN ／WR PORT2 PORT0 LATCH Bus Cycle MicroProcessor Part II

MCS-51 Family Overview Instruction Decoder ACCUMULATOR TEMP REG FLAG INSTRUCTION REGISTER AND DECODER ACCUMULA- TOR LATCH ARITHMETIC LOGIC UNIT BRANCH LOGIC CONDITION INT0 INT1 CARRY ACC TIMER …. … 1. Store the OP Code 2. Decoding 3. Output Control Signal DECIMAL ADJUST MicroProcessor Part II

MCS-51 Family Overview Arithmetic Logic Unit ACCUMULATOR TEMP REG FLAG INSTRUCTION REGISTER AND DECODER ACCUMULA- TOR LATCH ARITHMETIC LOGIC UNIT BRANCH LOGIC CONDITION INT0 INT1 CARRY ACC TIMER …. … Input : 1 or 2 x 8bit data Output : 8bit result data 1. +, - (carry) 2. Increment, Decrement 3. Bit Complement 4. Rotate Left/Right 5. Nibble Exchange 6. *, / DECIMAL ADJUST MicroProcessor Part II

MCS-51 Family Overview Accumulator ACCUMULATOR ACCUMULA- TOR LATCH TEMP REG ARITHMETIC LOGIC UNIT DECIMAL ADJUST INSTRUCTION REGISTER AND DECODER BRANCH LOGIC CONDITION FLAG INT0 INT1 CARRY ACC. TIMER … .... 1. Store Input Data 2. Store Result Data 3. Transfer data to Memory and I/O MicroProcessor Part II

MCS-51 Family Overview CPU Timing (I) Machine Cycle consists of six states ( 12 oscillator periods) OSC (xtal1) ALE STATE S1 S2 S S4 S5 S6 S1 S2 S3 S4 S5 S6 1-BYTE, 1-CYCLE Instruction (INC a ) READ NEXT OPCODE AGAIN READ OPCODE READ NEXT OPCODE ( DISCARD) 2-BYTE, 1-CYCLE Instruction (ADD a , #data ) READ NEXT OPCODE READ OPCODE READ 2nd BYTE MicroProcessor Part II

MCS-51 Family Overview CPU Timing (II) OSC (xtal1) ALE STATE S1 S2 S S4 S5 S6 S1 S2 S4 S3 S5 S6 READ NEXT OPCODE AGAIN 1-BYTE, 2-CYCLE Instruction (INC DPTR ) READ OPCODE READ NEXT OPCODE ( DISCARD ) MicroProcessor Part II

MCS-51 Family Overview CPU Timing (III) OSC (xtal1) ALE STATE S1 S2 S S4 S5 S6 S1 S2 S4 S3 S5 S6 1-BYTE, 2-CYCLE Instruction (MOVX) READ OPCODE NO FETCH NO FETCH READ NEXT OPCODE ( DISCARD ) ACCESS EXTERNAL MEMORY MicroProcessor Part II

MCS-51 Family Overview Memory Organization Logical Separation of Program and Data Memory PROGRAM MEMORY (READ ONLY) DATA MEMORY (READ/WRITE ONLY) FFFF FFFF Ext Ext 216 0FFF /EA=0 Ext /EA=1 Int FF Int Int 4KB =4096B Int 0000 00 / RD / WR / PSEN MicroProcessor Part II

MCS-51 Family Overview Program Memory After reset, the CPU begins execution from location 0000h The interrupt causes the CPU to jump to that location, where it commences execution of the service routine Ex) External Interrupt = 0003h The lowest 4K bytes of program memory can be either in the On-chip ROM or in an External ROM ( /EA (=External Access )) The read Strobe to external ROM, /PSEN, is used for all external program fetches. /PSEN is not activate for internal program fetches. MicroProcessor Part II

MCS-51 Family Overview Program Memory Internal Program Memory : Lower 4KB region of the program memory 0FFF Longer service routines can be jump instruction PROGRAM LOCATIONS 002B If an interrupt service routine is short enough ( as is often the case in control applications), it can reside entirely within that the 8-byte interval. 0023 001B INTERRUPT LOCATIONS 0013 8 BYTE 000B 0003 RESET 0000 MicroProcessor Part II

MCS-51 Family Overview Data Memory Internal Data Memory space is shown divided into three blocks, which are generally refereed to as the lower 128, the Upper 128, and SFR space Internal Data Memory Address are always 1 byte wide ( 256Byte ) FF Accessible by direct Addressing PORTS STATUS BIT CONTROL BIT TIMER REGISTERS STACK POINT ACCUMULATOR (ETC..) UPPER 128 Special Function Registers 80 7F Accessible by indirect Addressing only LOWER 128 00 Accessible by direct and indirect addressing MicroProcessor Part II

The Lower 128 Byte of internal RAM MicroProcessor Part II
MCS-51 Family Overview The Lower 128 Byte of internal RAM The Lower 128 Byte of internal RAM 3F ~ 7F STACK 20 ~ 2F BIT-ADDRESSABLE SPACE 11 18 ~ 1F BANK SELECT BIT IN PSW 10 10 ~ 17 4 BANKS OF REGISTER (R0~R7) 01 08 ~ 0F 00 00 ~ 07 MicroProcessor Part II

MCS-51 Family Overview 4 Banks Of Register 4 X 8 REGISTER BANK R7 R6 R5 R4 R3 R2 R1 R0 4th REG. BANK 3rd REG. BANK 2nd REG. BANK R7 R6 R5 R4 R3 R2 R1 R0 1st REG. BANK MicroProcessor Part II

Bit-Addressable Register MicroProcessor Part II
MCS-51 Family Overview Bit-Addressable Register 7F 7E 7D 7C 7B 7A 79 78 2Fh Boolean Instruction ( Bit Operation ) 77 76 75 74 73 72 71 70 2Eh AND, OR, CLEAR, SET COMPLEMENT, MOVE BIT ….. Ex) ANL CY, Bit Address CY Bit Address AND ANL CY, 27h.3 Before : CY (27h) After : CY 1 0F 0E 0D 0C 0B 0A 09 08 21h 07 06 05 04 03 02 01 00 20h MicroProcessor Part II

Special Function Register (SFR) - (I) MicroProcessor Part II
MCS-51 Family Overview Special Function Register (SFR) - (I) 1. Software Control/Operation ( Acc, B, DPTR, PSW, SP ) 2. Internal Unit Control MicroProcessor Part II

Special Function Register (SFR) - (II) MicroProcessor Part II
MCS-51 Family Overview Special Function Register (SFR) - (II) MicroProcessor Part II

MCS-51 Family Overview Special Function Register (SFR) - (III) - Software Control/Operation Acc : 8 Bit Accumulator ( Arith./Logical Operation) B : General Purpose Register : X , / DPTR : 16Bit Register , 8-bit accessable. ( using address pointer in the transmit External Data transfer ) PSW : 8 Bit -Register, ( carry, Overflow, Parity Flag, Selection of the Register Bank ) SP : Stack Point , 8-Bit Register MicroProcessor Part II

MCS-51 Family Overview Timer/Count : TH1, TL1, TH0, TL0, TMOD, TCON
Special Function Register (SFR) - (III) - Internal Unit Control Timer/Count : TH1, TL1, TH0, TL0, TMOD, TCON Serial Port : SBUF, SCON, PCON Interrupt control : IE, IP I/O Port : P0, P1, P2, P3 MicroProcessor Part II

Chap2 . The Instruction of 8051 Family
Instruction Set 5 Groups - 51 Instructions 1. Data Transfers Instructions 2. Arithmetic Instructions 3. Logical Instructions 4. Boolean Instructions 5. Jump Instructions MicroProcessor Part II

The Concepts of OPCODE & OPERAND Instruction Code 1 Byte Instr. OP Code Operand (Specification of the Operation) (Specification of the Address) The length of an Instruction depends on 1. The number of operands it involves 2. The Way it specifies each operands MicroProcessor Part II

Some Inst. Formats of the Intel 8085 Single-byte zero address Instruction Operand field 1 Operand field 2 Opcode Single-byte one address Instruction Single-byte two address Instruction Two-byte one address Instruction Three-byte one address Instruction MicroProcessor Part II

Every general-purpose computer has its own unique instruction. The Instruction Code is a group of bits that tell the computer to perform a specific operation. Operation Code : It define such operations as add, subtract, multiply, shift, and complement. Total number of operations obtained determines the set of machine operations. Opcode must consist of at least n bits for a given 2n (or less) distinct operations. Instruction (=Macro-Instruction) = The Sequences of Micro-Instruction MicroProcessor Part II

1. Data Transfer Instructions 1. The Immediate Addressing Mode 2. The Direct Addressing Mode 3. The Register Addressing Mode 4. The Register-Specific Addressing Mode 5. The Register Indirect Addressing Mode 6. The Register Indexed Addressing Mode MicroProcessor Part II

1.Data Transfer Instruction - The Immediate Addressing Mode The Immediate Addressing Mode : Immediate addressing, or perhaps more explicitly, immediate constant addressing, refers to the source being a constant embedded into code. Mov a , # ; { 74 01h } = { Opcode + Operand } Include Data Register(Acc, SFR), Memory Org 8000h ; set the origin mov a, #0h ; put 0 into the accumulator mov a, #11h ; put 11h into the accumulator mov a, #27 ; put 27(Dec) = 1bh into the accumulator Start Addressing : 8000h of external RAM The sequence of Accumulator : ??h > 00h > 11h > 1bh MicroProcessor Part II

1. Data Transfer Instruction - The Immediate Addressing Mode Ex ) MOV A , #33h MOV DPTR , #1234h DPTR PROGRAM MEMORY PROGRAM MEMORY ACC DPH DPL 33h 12h 34h 74 OP CODE 90 OP CODE 33 12 IMMEDIATE DATA IMMEDIATE DATA 34 MicroProcessor Part II

1. Data Transfer Instruction - The Immediate Addressing Mode Ex ) Org 8000h ; set the origin mov psw, #0 ; select register bank 0 mov r0, #0 ; put 0 into register0 mov r1, #1 ; put 1 into register1 mov psw, #8 ; select register bank 1 Org 8000h ; set the origin mov 70h, #0 ; put 0 into internal register 70 mov 71h, #1 ; put 1 into internal register 71 Org 8000h ; set the origin mov DPTR, #1234h ; place 12h into DPH and 34h DPL MicroProcessor Part II

1. Data Transfer Instruction - The Direct Addressing Mode The Direct Addressing Mode : The Direct addressing mode refers to specifying an internal data register or an SFR by its address. Org 8000h ; set the origin mov a, 70h ; copy contents of internal register 70h to a mov a, #0 ; clear the accumulator mov 90h, a ; copy the accumulator contents to SFR 90h MOV ……. , …….. Internal Data Memory  Acc, Reg .. Internal Data Memory  Internal Data Memory MicroProcessor Part II

1. Data Transfer Instruction - The Direct Addressing Mode Ex ) mov A , 33h mov 30h , R7 DATA MEMORY DATA MEMORY ACC R7 D1 DE 33h D1 DE 30h DATA DATA < Instr. Code > mov A , #33h : 74 33 mov A , 33h : E5 E0 MicroProcessor Part II

1. Data Transfer Instruction - The Direct Addressing Mode Ex ) mov 30h , 35h mov 06h , 00h PROGRAM MEMORY DATA MEMORY PROGRAM MEMORY DATA MEMORY DATA 85 30h D1 85 00h DE 30 06 35 00 35h D1 06h DE DATA MicroProcessor Part II

1. Data Transfer Instruction - The Direct Addressing Mode Ex ) Port 4 equ 0E8h ; port 4 Port 1 equ 090h ; port 1 Org 8000h ; set the origin mov a, Port4 ; copy the contents of port 4 (= E8h) mov Port1, a ; copy the acc. contents to contents of port 1 ljmp 8000h ; repeat MicroProcessor Part II

1. Data Transfer Instruction - The Register Addressing Mode The Register Addressing Mode : The Register addressing mode refers to either the source or the destination being one of the eight registers of the currently selected register bank. MOV PSW, # B ; BANK SELECT (BANK1) MOV A, #30h ; Immediate Addressing Mode MOV R1, A ; R1 = 30h MOV R3, #20h MOV R0, R1 ; REG  REG (X) MicroProcessor Part II

Cf ) Program Status Word (PSW) The PSW contains several status bit that reflect the current state of the CPU. CY AC F0 RS1 RS0 OV P PSW0 PARITY OF ACCUMULATOR SET BY HARDWARE TO 1 IF IT CONTAINS AN ODD NUMBER OF 1S, OTHERWISE IT IS RESET TO 0 PSW7 CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ALU OPERANDS PSW6 AUXILARY CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERANDS PSW1 USER DEFINABLE FLAG PSW5 GENERAL PURPOSE STSTUS FLAG PSW2 OVERFLOW FLAG SET BY ARITHMETIC OPERATIONS PSW4 REGISTER BANK SELECT BIT 1 PSW3 REGISTER BANK SELECT BIT 0 MicroProcessor Part II

1. Data Transfer Instruction - The Register-Specific Addressing Mode The Register-Specific Addressing Mode : Some instructions are specific to the registers used. inc a ; increase contents of accumulator ; 04h inc DPTR ; increase contents of DPTR ; A3h org 8000h ; set the origin mov a, #1 ; move the contents 1 into the accumulator mov 0E0h,#1 ; move the contents 1 into SFR E0h ljmp 0 ; return to the monitor MicroProcessor Part II

1. Data Transfer Instruction - The Register-Specific Addressing Mode mov a, #1 ; move the contents 1 into the accumulator PROGRAM MEMORY “take the following byte and place in the accumulator” = the accumulator being the destination is implicitly coded in the instruction 74 01 MicroProcessor Part II

1. Data Transfer Instruction - The Register-Specific Addressing Mode mov 0E0h, #1 ; move the contents 1 into SFR E0h PROGRAM MEMORY the following 2 bytes 75 first is the address of register E0 put the second byte to E0h ( = SFR ) 01 E0h 01 = SFR MicroProcessor Part II

1. Data Transfer Instruction - The Register Indirect Addressing Mode The Register Indirect Addressing Mode : The address of the source or destination is not given explicitly. Instead, the contents of a register is used as the target address. org 8000h ; set the origin mov PSW, #0 ; select register 0 mov R0, #78h ; move 78h into register 0 #1 ; set the register whose address is specified in ; the R0 register to the constant 1 ljmp 0 ; return to the monitor MicroProcessor Part II

1. Data Transfer Instruction - The Register Indirect Addressing Mode mov R0, # 40h mov mov R1, # 50h mov @R1, #ADh Acc DATA MEMORY DATA MEMORY 35 35 AD 40h 50h MicroProcessor Part II

1.Data Transfer Instruction - The Register Indirect Addressing Mode mov @R0, 40h DATA MEMORY 55 40h 55 R1 MicroProcessor Part II

Addressing Mode - The Source & Destination of MOV Instruction INTERNAL DATA MEMORY mov 77h, DPL 7Fh FFh SFR mov b, a 00h 80h mov a, 88h mov 33h, R7 R7 R6 R5 R4 R3 R2 R1 R0 REGISTERs Acc mov a, 77h mov 10h, 77h mov a, R3 MicroProcessor Part II

Addressing Mode - The Source & Destination of MOV Instruction mov 10h, 77h mov 33h, R7 #33h mov a, #33h mov 3Fh, #33h Direct Addressing Register R0 ~ R1 Indirect Addressing Immediate Data Acc MicroProcessor Part II

1. Data Transfer Instruction - The Register Indexed Addressing Mode The Register Indexed Addressing Mode In this mode, the source or destination address is obtained by adding the value held in the accumulator to the base address. The base address may either be the data pointer DPTR, or the program counter PC. Register Indirect Addressing @ Base Register + Index Register DPTR, PC Acc mov a + DPTR mov a + PC MicroProcessor Part II

1. Data Transfer Instruction - The Register Indexed Addressing Mode mov a + DPTR mov a , #1 mov DPTR, #1000h mov + DPTR PROGRAM MEMORY PROGRAM MEMORY Acc Acc 1000h 30 3A 1 31 DPTR + 1EADh 3F DPTR + 32 1E73 1000 33 Acc Acc 34 3F 31 MicroProcessor Part II

1. Data Transfer Instruction - The Register Indexed Addressing Mode Org 2000h mov a , #10h movc + PC PROGRAM MEMORY 2000h 74 Acc mov a , #10h 2001h 10 10h 2002h 83 movc a + Current PC 2003h PC 55h 2003h 2013h 55 MicroProcessor Part II

1. Data Transfer Instruction - The Stack Oriented Data Transfer The Stack Oriented Data Transfer : Another form of register indirect addressing is implemented with push and pop instructions. These instructions use the SFR stack pointer (SP) Org 8000h ; set the origin mov SP , #4Fh ; initialize stack point mov a, #45h ; put 45h in the accumulator push acc ; push the accumulator mov b, #0 ; clear the B register pop b ; pop top of stack into the B register push acc push a ; Note that the operand acc is the symbol define to be 0E0h. ; ( X ) : it uses the register-specific addressing mode. MicroProcessor Part II

1. Data Transfer Instruction - The Bit Oriented Data Transfer The Stack Oriented Data Transfer Micro-Controller often manipulates single-bit data signals ( Ex ) pushbutton , a motor driver, Bit-Addressable Access) Org 8000h ; set the origin mov C , P1.0 ; move the button state into carry flag mov P1.1, C ; move the carry flag to the LED ljump 8000h ; repeat Vcc .. P1.2 P1.1 P1.0 Architecture MicroProcessor Part II

2. Exchange Instruction Exchange Instruction : Exchange Instructions perform powerful two-way data transfers without the need for a temporary storage byte. Two Exchange operations : 1. Byte-wise XCH 2. Nibble-wise XCHD (exchange digit) XCH a , <Source> XCHD a , Ri R0~R7 Direct Address Mode Acc Source Acc Source Byte Nibble MicroProcessor Part II

2. Exchange Instruction XCH a XCH a , R5 a R5 a @R1 Before 15 78 Before 12 34 After 78 15 After 34 12 XCH a , 30h XCHD a a (30h) a @R1 Before Before A5 37 56 78 After After 37 A5 58 76 MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions INC/DEC Instruction : Register-specific, Register, Direct, Register Indirect Addressing : Loop Counters, Pointers Mnemonic : INC Source Operand : Source Data = Source Data + 1 DEC Source Operand : Source Data = Source Data - 1 INC a Acc CY AC OV P FF X Before After MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions DEC a Acc CY AC OV P X FF Before After INC 30h INC DPTR DEC DPTR DEC DPL DEC DPH MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions ADD/SUB Instructions 1. ADD a, Source Operand 2. ADDC a, Source Operand 3. SUBB a, Source Operand Acc Src Data CY Multi-Byte Adding Acc, R0~R7 @R0, XXh #XXh 16Bit C 8Bit C 8Bit C MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions Ex ) ADD a, #32h Acc CY AC OV P A PSW Before After Sign Bit (76h) (+) (32h) (+) (A8h) Over Flow Flag (+) + (+ ) -128 ~ + 127 Result ( - ) ? MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions Ex ) ADD @R1 = 62h Acc CY AC OV P E Before After Sign Bit (86h) (-) (62h) (+) (E8h) (-) + (+) = (-) O.K. Result ( - ) MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions Ex ) ADDC a, 50h Addr 50h = 4Eh Acc CY AC OV P A Before Sign Bit After (55h) (+) (4Eh) (+) (+) (A3h) Over Flow Flag -128 ~ + 127 For Multi-Byte Add Result ( - ) MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions Ex ) ADDC a, R5 R5 = 58h Acc CY AC OV P E Before Sign Bit After (E9h) (-) (58h) (+) (..) (41h) Over Flow Flag -128 ~ + 127 Result (+ ) MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions Ex ) SUBB R0 = 37h Barrow 0110 Acc CY AC OV P 1B Before After (53h) (+) (37h) (+) (+) (1Bh) (+) - (+) = (+) O.K. For Multi-Byte Sub Result (+ ) MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions Multiplication Instructions MUL AB B Acc B Acc MSB LSB OV Flag = Set ( if Acc > 255 ) mov a , #31h ; move the 31 into Accumulator mov b , #10h ; move the 10 into B register mul ab ; Acc X B B Acc B Acc 03 10 10 31 MSB LSB MicroProcessor Part II

2. Data Processing Instruction - Arithmetic Instructions Division Instructions B Result(portion) Remainder DIV AB Acc / B Acc OV Flag = Set ( if B Reg = 0 ) mov a , #118 ; move the 31 into Accumulator mov b , #5 ; move the 10 into B register div ab ; B / Acc B Acc Acc B / 3 17 76 5 MicroProcessor Part II

2. Data Processing Instruction - Logical Instructions Byte-wise Logical Operations Inst. Destination Source ANL ORL XRL CPL CLR SWAP Acc , Direct Addressing , Acc R0 ~ R7 .. Direct Addressing # Data Acc # Data MicroProcessor Part II

2. Data Processing Instruction - Logical Instructions CLR A CPL A CLR A CPL A (CLear Acc ) (ComPlement Acc) Before b (B5h) b (5Bh) After b (00h) b (4Ah) ANL Dest, Src ORL Dest, Src ORL a , R4 ANL 37h , # b Before (Acc) # b # b Before (37h) # b # b (R4) After (Acc) # b After (37h) # b MicroProcessor Part II

2. Data Processing Instruction - Logical Instructions XRL Dest, Src XRL a , @R0 XRL P1 , #51h Before (Acc) # b Before (P1) # b # b # b After (P1) # b After (Acc) # b MicroProcessor Part II

2. Data Processing Instruction - Logical Instructions RL Acc RR Acc (Rotate Acc Left ) (Rotate Acc Right ) MOV a , # 37h RL a MOV a , # 37h RR a a = # 73h a = # 73h MicroProcessor Part II

2. Data Processing Instruction - Logical Instructions RLC Acc RRC Acc (Rotate Acc & Carry Left ) (Rotate Acc & Carry Right ) CY CY CY Acc CY Acc Before After Before After MicroProcessor Part II

2. Data Processing Instruction - Logical Instructions SWAP Acc (SWAP Acc) Acc Before After MicroProcessor Part II

2. Data Processing Instruction - Boolean Instructions Bit Operation = Carry Flag ( CY ) = Bit Accumulator cf) Byte Operation = Accumulator Bit Operation CY Bit Addressable Range ANL C, Bit Address Ex) ANL C, 20h.5 ORL C, Bit Address Ex) ORL C, A.7 CPL C Ex) CPL C Bit Address Ex) CPL 23h.7 SET C Ex) SET C Bit Address Ex) SET 40h CLR C Ex) CLR C Bit Address Ex) CLR 28h.0 MicroProcessor Part II

2. Data Processing Instruction - Boolean Instructions Bit Transfer CY Direct Address MOV C, Bit Address Ex) MOV C, 20h.5 Before CY (20h) After CY MOV Bit Address, C Ex) MOV 26h.0, C Before CY (26h.0) After (26h.0) MicroProcessor Part II

2. Data Processing Instruction Program Counter On Power-On-Reset : PC is RESET ( 0000h ) 1 Byte Instruction Fetch : PC = Current PC + 1 The address pointer of next instruction Program Flow Control Instructions 1. Branch Instructions 2. Subroutine Calls 3. Interrupts MicroProcessor Part II

2. Data Processing Instruction - Unconditional Jump Instructions 1. Unconditional Jump Instructions 1. SJMP < Realtive Address > : Short Jump 2. AJMP < Address 11 > : Absolute Jump 3. LJMP < Address 16 > : Long Jump 4. JMP @A+DPTR : Long Jump ( Indexed Addressing ) MicroProcessor Part II

2. Data Processing Instruction - Unconditional Jump Instructions 1. SJMP < Realtive Address > : Short Jump Signed 8 Bit (-128 ~ +127) PROGRAM MEMORY SJMP 06h 051Eh 051Fh 0520h 80 06 Current PC ?? 0520h + 0526h 0526h MicroProcessor Part II

2. Data Processing Instruction - Unconditional Jump Instructions Org 0300h SJMP BOT … CAA : MOVE A, R1 BOT : INC A …. User : JMP Compiler ( If Range (-128 ~ 127 )) SJMP RANGE -128 ~ 127 MicroProcessor Part II

2. Data Processing Instruction - Unconditional Jump Instructions 2. AJMP < Address 11 > : Absolute Jump AJMP 01D2h 083Fh 0840h 0841h 21 01D2 = D2 ?? 0841 = Current PC 09D2h 09D2 <= 11 Bit Address => Jump range ( ~ 2KB ) Saving 1 Byte ( cf. LJMP : 2 Byte ) MicroProcessor Part II

2. Data Processing Instruction - Unconditional Jump Instructions 3. LJMP < Address 16 > : Long Jump LJMP 0A3Eh 0056h 0057h 0058h 02 3BYTE 0A PC : 0A3E 3E 0A3Eh 0A3Fh MicroProcessor Part II

2. Data Processing Instruction - Unconditional Jump Instructions Org 0300h LJMP BOT … CAA : MOVE A, R1 BOT : INC A …. User : JMP Compiler ( If Range : over -128 ~ 127 ) LJMP RANGE ~ xxx MicroProcessor Part II

2. Data Processing Instruction - Unconditional Jump Instructions 4. JMP @A+DPTR : Long Jump ( Indexed Addressing ) JMP @A+DPTR 03A7 73 Acc DPTR 0C 0410 + PC 041C MicroProcessor Part II

2. Data Processing Instruction - Conditional Jump Instructions 2. Conditional Jump Instructions 1. JZ < Relative Address > : 2. JNZ < Relative Address > : 3. JC < Relative Address > : 4. JNC < Relative Address > : 5. JB < Bit > , < Relative Address > : 6. JNB < Bit > , < Relative Address > : 7. JBC < Bit > , < Relative Address > : 8. CJNE A , Direct , < Relative Address > : 9. CJNE A, #Data , < Relative Address > : 10. CJNE Rn , #Data , < Relative Address > : 11. CJNE @Ri , #Data , < Relative Address > : 12. DJNZ Rn , < Relative Address > : 13. DJNZ Direct , < Relative Address > : MicroProcessor Part II

2. Data Processing Instruction - Call & Return Instructions 3. Call & Return Instructions 1. ACLL < Address 11 > : ( Range : 2KByte ) 2. LCALL < Address 16 > : ( Range : 64KByte ) 3. RET : Pop program counter off the stack 4. RETI : Pop program counter off the stack : and reset interrupt hardware. MicroProcessor Part II

Chap3. Timer Interrupt & Optimize
0FFF PROGRAM LOCATIONS Longer service routines can be jump instruction 002B RI+TI 0023 TF1 INTERRUPT TABLE 001B IE1 If an interrupt service routine is short enough ( as is often the case in control applications), it can reside entirely within that the 8-byte interval. 0013 TF0 8 BYTE 000B IE0 0003 RESET 0000 MicroProcessor Part II

Micro-Processor Part II Chap3. Timer Interrupt & Optimize TCON Register (MSB) (LSB) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 NAME Function Timer x over flow Flag Set by hardware on timer/counter overflow Cleared by hardware when processor vectors to interrupt routine TFx Timer x Run control bit Set/Cleared by software to turn timer/counter on/off TRx MicroProcessor Part II

Micro-Processor Part II Chap3. Timer Interrupt & Optimize TCON Register (MSB) (LSB) TF1 TR1 TF0 TR0 IE0 IE1 IT1 IT0 NAME Function Interrupt x Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed. IEx Interrupt 1 Type control bit Set/Cleared by software to specify Falling edge/low level triggered external interrupts ITx MicroProcessor Part II

Micro-Processor Part II Chap3. Timer Interrupt & Optimize TMOD Register - Operation Control (MSB) (LSB) GATE C/T M1 M0 M1 M0 TIMER TIMER2 GATE Gating Control When Set Timer/Counter “x”is enabled Only while “INTx”pin is high and “TRx” control pin is set When Cleared Timer “x” is enabled Whenever “TRx” control bit is set C/T Timer or Counter Selector Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from “Tx” input pin) MicroProcessor Part II

Micro-Processor Part II Chap3. Timer Interrupt & Optimize TMOD Register - Operating Mode Control (0 , 1, 2 ) (MSB) (LSB) GATE C/T M1 M0 TIMER TIMER2 M1 M0 Function 0 0 8048 TIMER : ”TLx” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter : “THx” and “TLx” are cascaded “THx” hold a value which is to be Reloaded into “TLx” each time it overflows 1 0 MicroProcessor Part II

Micro-Processor Part II Chap3. Timer Interrupt & Optimize TMOD Register - Operating Mode Control (Mode 3) (MSB) (LSB) GATE C/T M1 M0 TIMER TIMER2 Timer Function TL0 is an 8-bit timer-counter Controlled by the standard Timer 0 control bits Timer 0 TH0 is an 8-bit timer Only Controlled by Timer 1 control bits (TCON.TR1) Timer 1 Timer-counter 1 stopped MicroProcessor Part II

Timer Mode - Mode 0 Timer/Counter 1 Mode 0:13-bit Counter osc TL1 (5BITS) TH1 (8BITS) TF1 INTERRUPT T1 PIN CONTROL TR1 GATE MicroProcessor Part II

Timer Mode - Mode 1 Timer/Counter 1 Mode 1:16-bit Counter osc TL1 (8BITS) TH1 (8BITS) TF1 INTERRUPT T1 PIN CONTROL TR1 GATE MicroProcessor Part II

Chap3. Timer Interrupt & Optimize Timer Mode - Mode 2 Timer/Counter 1Mode 2:8-bit Auto-Reload osc TL1 (8BITS) TF1 INTERRUPT T1 PIN CONTROL RELOAD TR1 TH1 (8BITS) GATE MicroProcessor Part II

Chap3. Timer Interrupt & Optimize Timer Mode - Mode 3 Timer/Counter 0 Mode 3 : Two 8-bit Counters osc TL0 (8BITS) TF0 INTERRUPT T0 PIN CONTROL TR0 GATE 1/12 fOSC TH0 (8BITS) TF1 INTERRUPT TR1 CONTROL MicroProcessor Part II

Vector Table (Single Board Case) EXTERNAL PROGRAM MEMORY (ROM) In Our Single - Board Case, Actual interrupt service routine have to be exist in the data memory area (RAM address range: 8000H ~ 9FFFH) 0023 LJMP 80F9H TF1 001B LJMP 80F6H IE1 0013 INTERRUPT VECTOR TABLE LJMP 80F3H TF0 000B LJMP 80F0H IE0 0003 0000 MicroProcessor Part II

Micro-Controller 8051 Overview

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Micro-Controller 8051 Overview

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