1. MCS51 - part 1

2. Architecture MCS51 Addressing spaces & modes Instruction list
Lecture /47
Architecture MCS51 Addressing spaces & modes Instruction list

3. families: MCS151 MCS251 MCS48 family 8048/49/50 8020/21/22 6MHz
History /47
families: MCS151 MCS251
MCS48 family 8048/49/ /21/22 6MHz
MCS51 family 8051/52 12MHz
MCS96 family
1976
8085
1980
1983
1990

4. Architecture MCS /47
Features:
8-bit CPU;
built-in bit-processor;
255 instructions, including fast multiplying & dividing 1B×1B, 1B/1B;
built-in clock generator;
32 I/O lines;
built-in data memory SRAM of 128B;
built-in 4kB of program memory ROM (8051) or EPROM (8751);
64kB of external data memory space (RAM);
64kB of external program memory space (ROM,EPROM);
2 16b timers/counters;
built-in bidirectional serial port;
priority & vector interrupt system.

5. instr. reg. & decoder control unit
Architecture MCS /47
Structure of 8051
128B SRAM
reg. P2
RAM addr.reg.
PC incrementer
PC reg.
DPTR reg.
clock gen.
instr. reg. & decoder control unit
XTAL1 XTAL2
PSEN
ALE EA
RST
Acc
PSW
TMP1
TMP2
ALU
reg. B
reg. P1
PCON
SCON
SBUF
TCON
TH0
TL0
TH1
TL1
TMOD IP IE SP
interrupts, serial port timer/counters
reg. P0
reg. P3
4kB ROM
programme addr. reg.
P P1.0
P P3.0
P P0.0
P P2.0
Vcc GND
SFR

6. instr. reg. & decoder control unit
Architecture MCS /47
Structure of 8052
256B SRAM
reg. P2
RAM addr.reg.
PC incrementer
PC reg.
DPTR reg.
clock gen.
instr. reg. & decoder control unit
XTAL1 XTAL2
PSEN
ALE EA
RST
Acc
PSW
TMP1
TMP2
ALU
reg. B
reg. P1
PCON
SCON
SBUF
TCON
TH0
TL0
TH1
TL1
TMOD IP IE SP
interrupts, serial port timer/counters
reg. P0
reg. P3
8kB ROM
programme addr. reg.
P P1.0
P P3.0
P P0.0
P P2.0
Vcc GND
SFR
TH2
TL2
T2CON
RCAP2H
RCAP2L

7. Architecture MCS /47
Standard packages of 8051/52

8. 7Fh 78h bits direct addressable 07h 00h
Architecture MCS /47
Memory spaces of MCS51
0FFh
80h
bank #0
00h
bank #1
08h
bank #2
10h
bank #3
18h
7Fh h bits direct addressable 07h h
2Fh
20h
RAM
7Fh
30h
additional RAM
SFR
ROM ext. ROM int.
0000h
0FFFFh
external ROM
ROMMAX
EA=0
EA=1
0FFFFh
external RAM
0000h
internal RAM
program start address = 0000h
addresses = k*8+3 - interrupt vectors

9. Architecture MCS51 - working registers 9/47
Register banks
RAM bytes of address range: 00h..1Fh are available as 4 register banks: R0
00h: R1
01h: R2
02h: R3
03h: R4
04h: R5
05h: R6
06h: R7
07h:
bank00
08h:
09h:
0Ah:
0Bh:
0Ch:
0Dh:
0Eh:
0Fh:
bank01
10h:
11h:
12h:
13h:
14h:
15h:
16h:
17h:
bank10
18h:
19h:
1Ah:
1Bh:
1Ch:
1Dh:
1Eh:
1Fh:
bank11
Active bank number is store in bits RS1,RS0 in PSW.
Typical application of register banks is interrupt service..

10. Architecture MCS51 - direct addressable bits 10/47
They are stored in fragment of internal RAM and some SFR registers. They are accessible for bit instructions. They act as 1-bit logic variables.
Bits of RAM byte from 20h to 2Fh have direct addresses from 0 to 127, according to formula:
bit_addr = (byte_addr - 20h)*8 + position_in_byte
In SFR, direct addressable bits are placed in registers, which addresses equals multiple 8 (example 80h, C8h).

11. Architecture MCS51 - SFR 11/47
SFR - special function registers:
address space: from 80h to 0FFh;
registers control: access to built-in devices; processor work; interrupt system;
extensive address using in standard (8051) allows to design many different extensions (additional devices);
registers defined by Intel as 8051 standard, have the same addresses in other members of MCS51 family.
... -
PT2 BD
PS BC IP
B8h
bit not implemented
italic - additional object in 8052
address of direct addressable bit
register address in SFR
register name
bit name

12. Architecture MCS51 - SFR 12/47
P2.7 A7
P2.6 A6
P2.5 A5
P2.4 A4
P2.3 A3
P2.2 A2
P2.1 A1
P2.0 A0 P2
A0h
EA AF
- AE
ET2 AD
ES AC
ET1 AB
EX1 AA
ET0 A9
EX0 A8 IE
A8h
P3.7 B7
P3.6 B6
P3.5 B5
P3.4 B4
P3.3 B3
P3.2 B2
P3.1 B1
P3.0 B0 P3
B0h
- BF
- BE
PT2 BD
PS BC
PT1 BB
PX1 BA
PT0 B9
PX0 B8 IP
B8h
TF2 CF
EXF2CE
RCLKCD
TCLKCC
EXEN2CB
TR2 CA
C/T2 C9
CP/RL2C8
T2CON
C8h
CAh
RCAP2L
CBh
RCAP2H
CCh
TL2
CDh
TH2
CY D7
AC D6
F0 D5
RS1 D4
RS0 D3
OV D2
- D1
P D0
PSW
D0h
A.7 E7
A.6 E6
A.5 E5
A.4 E4
A.3 E3
A.2 E2
A.1 E1
A.0 E0 A
E0h
B.7 F7
B.6 F6
B.5 F5
B.4 F4
B.3 F3
B.2 F2
B.1 F1
B.0 F0 B
F0h

13. Architecture MCS51 - SFR 13/47
SBUF
SM0 9F
SM1 9E
SM2 9D
REN 9C
TB8 9B
RB8 9A
TI 99
RI 98
SCON
98h
P1.7 97
P1.6 96
P1.5 95
P1.4 94
P1.3 93
P1.2 92
P1.1 91
P1.0 90 P1
90h
8Dh
TH1
8Ch
TH0
8Bh
TL1
8Ah
TL0
GATE
C/T M1 M0
TMOD
89h
TF1 8F
TR1 8E
TF0 8D
TR0 8C
IE1 8B
IT1 8A
IE0 89
IT0 88
TCON
88h
SMOD -
GF1
GF0 PD
IDL
PCON
87h
83h
DPH
82h
DPL
81h SP
P0.7 87
P0.6 86
P0.5 85
P0.4 84
P0.3 83
P0.2 82
P0.1 81
P0.0 80 P0
80h

14. Architecture MCS51 - SFR - PSW 14/47
CY D7
AC D6
F0 D5
RS1 D4
RS0 D3
OV D2
- D1
P D0
PSW
D0h
CY - carry flag
AC - auxiliary carry flag (during adding from bit 3rd to bit 4th)
F0 - user flag
OV - arithmetic overflow flag
P - parity flag (parity of ones in ACC)
RS1,RS0 - register bank select bits: RS1,RS0 = active bank
There is no zero flag! Conditional jump instructions: JZ, JNZ directly check the accumulator.

15. Architecture MCS51 - SFR - A, B 15/47
Used by ALU. It contains direct addressable bits. Used during access to external data memory.
A.7 E7
A.6 E6
A.5 E5
A.4 E4
A.3 E3
A.2 E2
A.1 E1
A.0 E0 A
E0h
B.7 F7
B.6 F6
B.5 F5
B.4 F4
B.3 F3
B.2 F2
B.1 F1
B.0 F0 B
F0h
Additional working registers. Use in multiplication and dividing instructions. It contains direct addressable bits.

16. Architecture MCS51 - SFR - SP i stos 16/47
Addresses the top of stack - points the last written byte.
After reset it has value 07h !
Stack
Acts only in internal RAM (! limited area). Writing to stack moves the top of the stack to the higher addresses, reading - vice versa. ! Writing can cause overlapping the stack on lowest RAM addresses.
2Bh B:
11h A:
58h
SP: x
59h:
0Dh
58h:
34h
57h:
5Ah:
RAM
stack
PUSH B
POP A
stack
58h
2Bh
stack
59h
2Bh

17. MCS51 acting - adressing modes 17/47
Addressing modes for byte-operands
immediately
instr. code
argument
mov r6,#130
register
operand
instr. code
Rx:
mov a,r6
direct
instr. code
operand
address
intern. RAM
inc 20h

18. MCS51 acting - adressing modes 18/47
register indirect
int./ext. RAM
address8b
instr. code
operand
R0/R1:
address16b
DPTR:
ext. RAM
mov
movx

19. MCS51 acting - adressing modes 19/47
index-relative
PC/DPTR: d
instr. code
operand
ROM 
base A:
movc movc
Addressing mode for bit-operands
direct
instr. code
internal RAM
mov c,20h
address

20. MCS51 acting - adressing modes 20/47
ROM ext. ROM int.
0000h
0FFFFh
external ROM
ROMMAX
EA=0
EA=1
0FFh
80h
bank #0
00h
bank #1
08h
bank #2
10h
bank #3
18h
7Fh h bits direct addressable 07h h
2Fh
20h
RAM
7Fh
30h
additional RAM
SFR
register indirect
direct
register
bit-direct
register indirect by DPTR
register indirect by R0/R1
external RAM
internal RAM
index-relative
addressing modes - ranges of usage

21. Instruction list MCS /47
1. Arithmetic instructions

22. Instruction list MCS /47

23. Instruction list MCS /47

24. Instruction list MCS /47

25. Instruction list MCS /47
2. Logic instructions

26. Instruction list MCS /47

27. Instruction list MCS /47

28. Instruction list MCS /47
Example:

29. Instruction list MCS /47
3. Rotation instructions

30. Instruction list MCS /47
4. Bit instructions

31. Instruction list MCS /47
5. Transfer instructions

32. Instruction list MCS /47

33. Instruction list MCS /47

34. Instruction list MCS /47

35. Instruction list MCS /47

36. Instruction list MCS /47
6. Jump instructions

37. Instruction list MCS /47

38. Instruction list MCS /47
7. Call & return instructions

39. Instruction list MCS /47
8. Influence of instructions on PSW state

40. MCS51 - programming examples 40/47

41. MCS51 - programming examples 41/47

42. MCS51 - programming examples 42/47

43. MCS51 - programming examples 43/47

44. MCS51 - programming examples 44/47

45. MCS51 - programming examples 45/47

46. MCS51 - programming examples 46/47
Case „safe”:
state of T0: executed instruction:
8877h MOV R1,TH0
8878h
MOV R0,TL0
R1R0=8878h
Case „critical”:
state of T0: executed instruction:
88FFh MOV R1,TH0
8900h
MOV R0,TL0
! R1R0=8800h - error

47. MCS51 - programming examples 47/47