1. Silicon Stripixel Detector Status Rachid Nouicer Brookhaven National Laboratory (BNL) DOE Review of the PHENIX VTX Detector, June 2 nd, 2009 1. Executive Summary 2. Current Status Upgrade with Silicon Vertex Tracker

2. June 2 nd, 2009 rachid.nouicer@bnl.gov 2 Silicon module (ROC + Sensor + SVX4) Readout Control Chips (RCC) Bus Cable: Ladder-Data Transfer Board (LDTB) Front-End Module (FEM) WBS: 1.1 Stave

3. June 2 nd, 2009 rachid.nouicer@bnl.gov 3 Executive Summary I: - Silicon Module: assembly issues of the ROC-3 have been solved Today: Pre-production (8 modules) 3 silicon modules readout simultaneously June 2008: One silicon module with ROC-3 The silicon module gave good performance results  starting mass production Channel Number (128 channels x 12 chips) Raw ADC distributions ADC distributions corrected event-by-event pedestal subtraction Raw ADC distributions

4. June 2 nd, 2009 rachid.nouicer@bnl.gov 4 Executive Summary II: Readout Card (ROC): - Pre-production boards successfully tested - Good performance and reproducible - Mass production ordered. Readout Control Chips (RCC): pre-production boards worked and final design completed. Bus cable: pre-production worked and ready for production Ladder-Data Transfer Board (LDTB): prototype using LVDS communication worked. Fiber-based version design complete. Front-End Module (FEM): - Current using old prototype (worked). - Design on pre-production in final phase - Data Interface boards and crate ordered.

5. June 2 nd, 2009 rachid.nouicer@bnl.gov 5 Executive Summary III: - Assembly: 1.Silicon module mass production a)Assembly fixtures (32 pieces) were completed. They were used in pre-production silicon modules b)Production will be done at FNAL and the setups were installed c)Manpower identified and trained d)ROC ordered  We are ready for the mass production 2.Stripixel ladder a)Conceptual design completed by VTX and the drawings were delivered to HYTEC b)Stave: final design nearly complete c)Assembly fixtures and assembly machine are in progress d)Manpower were identified

6. June 2 nd, 2009 rachid.nouicer@bnl.gov 6 Current Status

7. June 2 nd, 2009 rachid.nouicer@bnl.gov 7 Outline (Progress Timeline) ➮ Reminder: Status at the Last Review (June 9, 2008) ➮ Performance Results of Silicon Module Using ROC-3  Response to electrons from 90 Sr beta source  Response to muons from cosmic-rays  Response to proton beam at 120 GeV ➮ Performance Results of Silicon Module Using ROC-3prime ➮ Performance Results of Silicon Module Using Pre-product. ROC  Electrical ladder tests ➮ Status of the Stripixel Detector Readout ➮ Preparation for Silicon Module Mass production ➮ Current Status of the Stripixel Ladder  Conceptual design of stripixel ladder ➮ Schedule ➮ Summary of the Current Status

8. June 2 nd, 2009 rachid.nouicer@bnl.gov 8 Summary II Silicon Modules using ROC-3 were built – Pedestal distributions and sensitivity to digital activity is much improved – Pedestal distribution of the module #3 is quite encouraging. – We need to make more modules to reliably reproduce good modules – Study sensitivity of the pedestal distribution by removing some components. This will help to design pre-production ROC that is easier for automatic assembly Cosmic ray test: – Cosmic ray hits have successfully detected by silicon module ROC-3 – Good correlation between X and U strips has been observed – Signal/Noise has been measured: MIP/noise = 10.4 More details about the next steps for the Stripixel Detector will be present in the next talk by Yasuyuki Akiba Reminder: Status at the Last Review (June 9, 2008 ) ➮ Reminder: Status at the Last Review (June 9, 2008 ) Slide from Last Review, June 2008

9. June 2 nd, 2009 rachid.nouicer@bnl.gov 9 The ROC-3 board is not intended as production board ROC-3 board has the analog power plan continuous ROC-3 board thickness of each power and ground layers is 35  m Pedestal distribution Silicon module using ROC-3 Raw ADC Reminder: Status at the Last Review (June 9, 2008 ) ➮ Reminder: Status at the Last Review (June 9, 2008 ) Channel Number (128 channels x 12 chips) Slide from Last Review, June 2008

10. June 2 nd, 2009 rachid.nouicer@bnl.gov 10 Reminder: Status at the Last Review (June 9, 2008 ) ➮ Reminder: Status at the Last Review (June 9, 2008 ) Text from the review report The primary focus of this review was on the technical difficulties with the Read-Out Card (ROC) for the strip- pixel system… Performance of the ROC3 is encouraging but needs additional samples to be fully convincing… The planned beam test this summer should make both the MIPs level and efficiency measurements much more complete. The completed board is difficult to assemble, and the performance of the single board tested may not be reproduced in a production run.

11. June 2 nd, 2009 rachid.nouicer@bnl.gov 11 ➮ Performance Results of Silicon Module Using ROC-3  Response to electrons from 90 Sr beta source  Response to muons from cosmic-rays  Response to proton beam at 120 GeV (FNAL) For details see: PHENIX VTX Collaboration, Journal of Instrumentation (JINST), 4 P04011 (2009) http://www.iop.org/EJ/abstract/1748-0221/4/04/P04011

12. June 2 nd, 2009 rachid.nouicer@bnl.gov 12 Silicon Module Using ROC-3: Silicon Module Using ROC-3: Excellent Charge Sharing For x channels For u channels Response to Electrons from 90 Sr Beta Source ➮ Response to Electrons from 90 Sr Beta Source HV(V) Pedestal 1  MPV S/N 2009.4187.89.3 HV(V) Pedestal 1  MPV S/N 2009.4191.29.7

13. June 2 nd, 2009 rachid.nouicer@bnl.gov 13 Top module is rotated so that the read-out region overlaps. Scintillators Sensors Response to Muons from cosmic-rays ➮ Response to Muons from cosmic-rays The tracks have been observed from cosmic-ray

14. June 2 nd, 2009 rachid.nouicer@bnl.gov 14 Response to Proton Beam at 120 GeV (FNAL) ➮ Response to Proton Beam at 120 GeV (FNAL) Profile of the proton beam Pixel layers Stripixel layers Proton beam at 120 GeV Charged Sharing Principal of two-dimensional position sensitivity based on charge sharing works

15. June 2 nd, 2009 rachid.nouicer@bnl.gov 15 Response to Proton Beam at 120 GeV (FNAL) ➮ Response to Proton Beam at 120 GeV (FNAL) HV(V) Pedestal 1  MPV S/N 2009.698.610.3 For x channels For u channels HV(V) Pedestal 1  MPV S/N 20010.1102.210.1 Signal-to-Noise Ratio

16. June 2 nd, 2009 rachid.nouicer@bnl.gov 16 Response to Proton Beam at 120 GeV (FNAL) ➮ Response to Proton Beam at 120 GeV (FNAL) Single Event Tracking: Linear Fit Track

17. June 2 nd, 2009 rachid.nouicer@bnl.gov 17 Response to Proton Beam at 120 GeV (FNAL) ➮ Response to Proton Beam at 120 GeV (FNAL) - Residual distribution (position resolution) X-stripixel 0.42 x 80 (  m) = 33.6 (  m) U-stripixel 0.44 x 80 (  m) = 35.2 (  m) - from the RMS values (tracks are defined by layers 1 and 3). - Tracking efficiency (detection efficiency) X-stripixel: 99.5 +/- 0.2 % U-stripixel: 98.9 +/- 0.2 % Tracking efficiency very good

18. June 2 nd, 2009 rachid.nouicer@bnl.gov 18 ➮ Performance Results of Silicon Module Using ROC-3prime ROC-3prime is made ROC-3prime is made  Improve manufacturability of ROC-3  Effect of ground / power layer thickness on noise

19. June 2 nd, 2009 rachid.nouicer@bnl.gov 19 ➮ Performance Results of Silicon Module Using ROC-3prime Pedestal distribution 2 modules: thickness power and ground layers 1/4 oz Cu 1 module: thickness power and ground layers 1/2 oz Cu This module has thickness 1/2 oz Cu Thickness 1/4 oz Cu: For x : S/N= 94.0 / 9.7 = 9.7 For u : S/N= 92.3 / 9.6 = 9.6 This module has thickness 1/2 oz Cu Source test Silicon module using ROC-3prime Good performance as ROC-3

20. June 2 nd, 2009 rachid.nouicer@bnl.gov 20 ➮ Performance Results of Silicon Module Using Pre-Production ROC

21. June 2 nd, 2009 rachid.nouicer@bnl.gov 21 ➮ Performance Results of Silicon Module Using Pre-production ROC  First Stripixel Ladder on Aluminum Stave 8 silicon modules - Bottom View of the ppROC - Zoom on one silicon module - Stripixel Ladders using aluminum staves - Bottom View of the ppROC

22. June 2 nd, 2009 rachid.nouicer@bnl.gov 22 ➮ Performance Results of Silicon Module Using Pre-production ROC - Photograph of the readout chain used for the ladder electrical tests  Stripixel ladder Readout Chain FEM LDTBBus cable Silicon modules RCCs Top View Bottom View FPGA chip

23. June 2 nd, 2009 rachid.nouicer@bnl.gov 23 ➮ Performance Results of Silicon Module Using Pre-production ROC - Photograph of electrical test setup and manpower:  Electrical ladder tests Front-End Module (FEM) Dark Box Ladder-Data Transfer Board (LDTB) Stripixel Ladder Temperature probes Akitomo E. Manabu T.Steven K. Alan D.

24. June 2 nd, 2009 rachid.nouicer@bnl.gov 24 ➮ Performance Results of Silicon Module Using Pre-production ROC  Electrical ladder tests: 3 modules readout simultaneously Without event-by-event pedestal subtraction Module 1 Module 2 Module 3 Front View Bottom View RCC issue

25. June 2 nd, 2009 rachid.nouicer@bnl.gov 25 ➮ Performance Results of Silicon Module Using Pre-production ROC  Electrical ladder tests: 3 modules readout simultaneously With event-by-event pedestal subtraction Module 1 Module 2 Module 3 Front View Bottom View ppROC module Pedestal  = 9.3 Better than ROC3 ppROC module Pedestal  = 9.3 Better than ROC3 ppROC module Pedestal  = 9.2 Better than ROC3

26. June 2 nd, 2009 rachid.nouicer@bnl.gov 26 ➮ Status of the Stripixel Detector Readout

27. June 2 nd, 2009 rachid.nouicer@bnl.gov 27 ROCs: pre-production boards successfully tested. Minor changes incorporated into layout of production boards (ordered). RCCs: rigid-flex boards: pre- production boards tested. Minor layout changes incorporated into final design (completed). Front-End Module (FEM): Continuing to use old prototype. Design on pre-production prototype far along. Data Interface boards and crate ordered. ➮ Status of the Stripixel Detector Readout Bus Cable: pre-production prototype tested. Only expected change is addition of a couple of inches in length. Ladder-Data Transfer Board (LDTB): prototype using LVDS communication successfully tested. Fiber-based version design complete.

28. June 2 nd, 2009 rachid.nouicer@bnl.gov 28  Status of Production ROC Only minor changes to layout have been done: –Relocate components to reduce interference –Modified routing to improve yield Production boards have been ordered (Hughes) Delivery: –40 boards: 1st Article – 15 business days from receipt PO (expected by the end of June ) –250 boards: split delivery – Hughes will purchase all passive components ➮ Status of the Stripixel Detector Readout

29. June 2 nd, 2009 rachid.nouicer@bnl.gov 29 Preproduction Prototype Modules Successfully Tested Rigid-flex geometry, to allow mounting on a realistic ladder. Final Design (complete) required modest layout Changes. Preproduction Final RCC Firmware Successfully Implemented  Faster readout clock  Drop channel data  Allow readout all ROCs in parallel  Fully triplicated Revisited Technology Choice (FPGA not ASIC):  Status of Production RCC ➮ Status of the Stripixel Detector Readout

30. June 2 nd, 2009 rachid.nouicer@bnl.gov 30 Revisited Technology Choice (FPGA not ASIC): - Report available at: http://www.phenix.bnl.gov/WWW/publish/obrien/reviews/VTX_June2009/VTX_Review2009_page.htm http://www.phenix.bnl.gov/WWW/publish/obrien/reviews/VTX_June2009/VTX_Review2009_page.htm ➮ Status of the Stripixel Detector Readout From Vince’s report: “ Conclusions/Recommendations - The expected NIEL dose is not a concern for an FPGA implementation of the RCC. - Soft SEUs should be mitigated to negligible levels with triplication of the RCC logic. - If some RCCs are lost due to excessive TID, or hard SEUs, they could be replaced at a tiny fraction of the cost of the ASIC solution… - I would recommend changing the project design to incorporate an FPGA-based RCC.”

31. June 2 nd, 2009 rachid.nouicer@bnl.gov 31  Status of the Bus Cable Pre-production Prototype Designed And Tested  Design incorporated pre-bent sections between each ROC to eliminate mechanical tolerance concerns.  Final design will require only slightly longer length (few inches beyond 21” tested length). ➮ Status of the Stripixel Detector Readout

32. June 2 nd, 2009 rachid.nouicer@bnl.gov 32  Ladder-data Transfer Board (LDTB) - Non-fiber version implemented: it worked - Fiber version design essentially complete –Ordering components –Board order (1-week turnaround) awaiting tests of fiber link (can be tested with Data Interface Boards (DIB) alone). ➮ Status of the Stripixel Detector Readout

33. June 2 nd, 2009 rachid.nouicer@bnl.gov 33 ➮ Status of the Stripixel Detector Readout  Front-End Modules (FEM) Consist of: – A VME-standard crate/backplane (Wiener catalog item). – A Controls Interface Board (CIB) for slow controls and timing system interface – 20 Data Interface Boards (DIBs) which pass slow controls and timing data to each ladder, and send event data from a given ladder to the corresponding Data Collection Module Need 2 for final system. Design Undergoing Final Reviews: DIB Layout and CIB Layout

34. June 2 nd, 2009 rachid.nouicer@bnl.gov 34 ➮ Preparation for Silicon Module Mass Production

35. June 2 nd, 2009 rachid.nouicer@bnl.gov 35 - All fixtures for silicon module assembly are ready and there were used to build the silicon modules of ladder for electrical test: designed at BNL and fabrication by BNL/SBU shops Silicon sensor positioning and alignment c) SVX4 chips pick-up and positioning a) SVX4 chips positioning b) SVX4 chips pick-up Transportation boxes ➮ Preparation for Assembly of Silicon Module Mass production

36. June 2 nd, 2009 rachid.nouicer@bnl.gov 36 SOW with FNAL has been established (done) - wire-bonding, encapsulation of the ROC-SVX4-Sensor and precision placement of the silicon sensor (FNAL) - Mounting SVX4 on ROC (VTX manpower) - Testing (VTX manpower) Team: Tammy Hawke (FNAL, wire-bonding), Mike Herren (FNAL, encapsulation), Bert Gonzalez (FNAL, trained on sensor placement), Steve Kaneti (SBU, trained on SVX4 placement), Manabu Togawa (RBRC, testing) + Paul Kline (SBU) and Rachid Nouicer (BNL, training people and ensuring success). we have summer students from SBU and ISU involve at different stage of the detector construction ➮ Preparation for Assembly of Silicon Module Mass production - We have also BNL-PHENIX technical support Steven K. & Rachid N. Bert G. Mike H. Tammy H.

37. June 2 nd, 2009 rachid.nouicer@bnl.gov 37 Tests and assembly steps for silicon modules mass production Step 1: (Steven K.) - Inventory of the ROC when they arrive to FNAL - Simple electrical test - Visual inspection for each ROC Step 2: (Steven K.) - Mounting the SVX4 chips on the good ROC - Documenting and introducing the SVX4 chips ID# and SVX4 location in the database Step 3: (Tammy H.) - Inspect the SVX4s chips mounting on the ROC - Wire bond the SVX4 chips to the ROC Step 4 (Manabu T.): - Test the ROC with SVX4 chips - Test results will go to the database and documentation logbook - decision good or bad ➮ Preparation for Assembly of Silicon Module Mass production

38. June 2 nd, 2009 rachid.nouicer@bnl.gov 38 Step 5: (Bert G.) - Inspect the board - Mount and align the sensor on the ROC - Document the information in logbook Step 6: (Tammy H.) - Inspect the ROC with sensor - Wire bond sensor to the SVX4 chips Step 7: (Manabu T.) - test he silicon module (no encapsulation) - test results will go to the database and documentation logbook - decision good or bad Step 8: (Mike H.) - Encapsulation the silicon of silicon module (based on VTX drawings) Step 9: (Manabu T.) - test the silicon module ( with encapsulation) - test results will go to the database and documentation logbook - decision good or bad - ship the silicon modules on the aluminum stave to BNL ➮ Preparation for Assembly of Silicon Module Mass production

39. June 2 nd, 2009 rachid.nouicer@bnl.gov 39 ➮ Current Status of the Stripixel Ladder

40. June 2 nd, 2009 rachid.nouicer@bnl.gov 40 ➮ Conceptual Design of the Stripixel Ladder  Done at BNL Readout Bus

41. June 2 nd, 2009 rachid.nouicer@bnl.gov 41 ➮ Current Status of the Stripixel Ladder  Drawings of the Conceptual design submitted to HYTEC For the Task Order #1: WBS 2.1.1 For HYTEC progress on the stripixel stave and barrel configuration see next talks by Walter Sondheim.

42. June 2 nd, 2009 rachid.nouicer@bnl.gov 42 ➮ Preparation for the Assembly of Stripixel Ladder Conceptual design completed by VTX Drawings of the conceptual design delivered to HYTEC Assembly fixtures design and fabrication are in process Assembly machine is in purchasing process Production will done at the VTX assembly lab. at BNL Manpower identified (different than silicon module assembly): - Team: Kieran Boyle (RBRC, silicon modules mounting on the stave), Stephan Bathe (RBRC, silicon modules mounting on the stave), Swadhin Taneja (SBU, silicon modules and ladder tests), Lei Ding (ISU, silicon modules and ladder tests), Andrew Manion (SBU), Sookhyn Lee (SBU) and Rachid Nouicer (BNL, training people and ensuring success).  We have also BNL-PHENIX technical support

43. June 2 nd, 2009 rachid.nouicer@bnl.gov 43 ➮ Summary of the Current Status All technical issues of ROC-3 silicon modules raised in the previous review have been solved.  Good performance have been obtained  Reproducibility of the good results is demonstrated  Mass production of ROC ordered Full chain of read-out (ROC+RCC+Bus+LDTB+FEM) worked  ROC: mass production ordered  RCC: final design completed  Bus cable: ready to go  LDTB: worked, fiber version design completed  FEM: design final phase Assembly of silicon modules of mass production ready to go Assembly of the stripixel ladder is in progress

44. June 2 nd, 2009 rachid.nouicer@bnl.gov 44 ➮ Schedule Silicon module assembly Ladder assembly