1. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Real-time data sparsification of MAPS detectors for HEP experiments and beyond Marcin Jastrzab (Como University, AGH Krakow) Angelo Cotta Ramusino (INFN Ferrara) Massimo Caccia (Como University, INFN Milano) Antonio Bulgheroni (INFN Milano) et al. jastrzab@agh.edu.pl

2. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Outline Motivation for data sparsification Motivation for data sparsification Solutions for sparsification implementation Solutions for sparsification implementation Monolithic Silicon Pixel Detectors – MAPS Monolithic Silicon Pixel Detectors – MAPS DAQ applications DAQ applications DAQ system architecture DAQ system architecture Preliminary results Preliminary results Future plans Future plans

3. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Motivation for data sparsification High data rate from the state-of-the-art silicon sensors High data rate from the state-of-the-art silicon sensors High granularity - large number of sensor channels to be readout High granularity - large number of sensor channels to be readout Low sensor occupancy often non exceeding a few % Low sensor occupancy often non exceeding a few % As an example let us consider the pixel sensor being readout @ 40MHz frequency. In many cases the sensor area is divided by 4 quadrants (columns) readout in parallel to increase the readout speed and reduce the integration time. In such a case the bandwidth necessary to transfer of the data is ~320MB/s for one detector only! The most popular interfaces characteristics: Ethernet: 1Gbit/s (125MB/s), 10Gbit/s (1.25GB/s) Ethernet: 1Gbit/s (125MB/s), 10Gbit/s (1.25GB/s) VME 64x: up to 160MB/s VME 64x: up to 160MB/s USB 2.0: 60MB/s USB 2.0: 60MB/s FireWire 800: 100MB/s FireWire 800: 100MB/s

4. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Motivation for data sparsification Sparsification offers the possibility to avoid the overhead and run at the full speed without dead- time. Data storage volume becomes much less important issue. Instead of using equipment computer farm, the data is being reduced at the DAQ level.

5. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Computer farm on-line sparse data identification Computer farm on-line sparse data identification DAQ based sparse data recognition – hardware (Atlas DAQ, EUDRB (EUDET project)) DAQ based sparse data recognition – hardware (Atlas DAQ, EUDRB (EUDET project)) On-chip implementation (SUZE-01 (IPHC/Strasbourg), Deep N-well 130nm (Pavia,Bergamo,Pisa,Bologna) – token architecture by R. Yarema (FNAL). On-chip implementation (SUZE-01 (IPHC/Strasbourg), Deep N-well 130nm (Pavia,Bergamo,Pisa,Bologna) – token architecture by R. Yarema (FNAL). Sparsification – possible solutions Basically there are 3 feasibile solution for sparsification algorithm implementation

6. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden MAPS – Monolithic Active Pixel Sensors Sparsification is not simple. Especially because algorithm results, reduced data volume and high speed have not to affect the quality of the recorded information. The sensor used in the measurements is a Mimosa 5 CMOS by LEPSI (IPHC Strasbourg). The charge carrier generated in the epitaxial layer 15  m thick - signal (~80 e-h pairs/  m). MAPS in CMOS technology has been pioneered in LEPSI in the late 90’s

7. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden MAPS – Monolithic Active Pixel Sensors The charge collection mechanism in CMOS MAPS sensors is based on thediffusion mechanism. The sensitive volume is not depleted and charge cluster spreads over ~ 50  m. Detector pixel size for Mimosa 5 sensor = 17  m. Collected charge vs. No of pixels in cluster

8. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden DAQ applications The DAQ system based on the Altera FPGA chip (EUDRB) is being used in the EUDET ILC project (see the details on the subsequent slides and the EUDET presentation). EUDRB is a base DAQ system for the EUDET telescope composed of 6 planes for high precision particle tracking. The zero suppresion mechanism has been implemented for MimoStar2, MimoTel and Mimosa18 sensor. The result obtained at DESY in August 2007 Eudet telescope

9. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden DAQ applications Tritium samples imaging with Mimosa 5 sensor has been done using Sucima Imager DAQ system, developed during Sucima EU project. Tritium imaging relies on single particle interaction measurement and 10 5- 10 6 frames are to be collected to obtain good quality image. Seed pixel signal distribution Ring 3 (3x3 crown) signal distribution

10. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden DAQ applications Image of the RPA506 standard acquired with the MIMOSA5 sensor over a 2 hours exposure time Ring 5 (5x5 crown) signal distribution

11. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden DAQ (EUDRB) Architecture The EUDET Data Reduction board was developed at INFN-Ferrara in collaboration with University of Insubria-Como and INFN-Roma 3 to read out Monolithic Active Pixel Sensors (MAPS). EUDRB is based on ALTERA CycloneII FPGA chip (clock rate: 80MHz). Two readout modes: Zero Suppressed readout to minimize the readout dead-time while in normal data taking. Non Zero Suppressed readout of multiple frames for debugging or off-line pedestal and noise calculations The EUDRB has been so far employed with the IPHC MIMOSA-5, MIMOSTAR 2 and MIMOTel devices.

12. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden DAQ (EUDRB) Architecture The FPGA handles the operations related to data collection, trigger servicing and I/O port interfacing with sequencers and logic blocks described in VHDL code or schematic diagrams. Ovierview of Data Flow for ZS operation of EUDRB

13. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden DAQ (EUDRB) Architecture EUDRB performs in ZS mode fetching of “hit” data without stopping detector scan and frame buffer update. Four firmware submodules perform the “hit”extraction in parallel (CDS and comparison with threshold after perdestal subtraction), one for each submatrix). This processor controls local FIFOs to store hit information until the output FIFO is available for receiving a new event data packet. The event data packet contains “hit” signal amplitude and pixel address encompassed within a Header and a Trailer. EUDRB contains NIOS II, 32 bit “soft” microcontroller (clock rate: 40Mz) implemented in the FPGA for „on board diagnostics” and remote configuration of the FPGA via RS-232, VME, USB2.0

14. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden EUDRB Cluster Search ZS Architecture The Cluster Search algorithm has been implemented into the EUDRB DAQ using VHDL code. The EUDRB equipment as a external FIFO memory together with the NIOS II processor external memory are the necesessary for the seed driven cluster search algorithm. The architecture of the ZS firmware is build in such a way that the cluster search is being done during the current detector readout and the data memory is being updated for four quarters independently. In the same time, the pixels hit (clusters) during the previous readout is being transfered to the output FIFO buffer to be sent out to the storage. The visualization of the implemented mechanism is shown on the next slide.

15. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Seed pixel address FIFO Cluster builder 3x3 or 5x5 pixels Current framePrevious frame Noise Pedestal DATA MEMORY DETECTOR MATRIX scan N Single DATA MEMORY cell CLUSTER PIXEL FLAG MEMORY DETECTOR MATRIX scan N+1 DATA MEMORY – FLAG MEMORY ADDRESS BUS OUTPUT FIFO MEMORY SIGNAL? DATA MEMORY EUDRB Cluster Search ZS mechanism

16. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Cluster Search ZS preliminary results The Cluster Search algorithm is being commissioned and the very preliminary results has been obtained. The mesaurements with IR laser, 3 H samples and the test beam is foreseen. Test setup with PLS 500 Picoquant, fast LED head system has been performed. PLS 500 – signal frequency 1MHz, emmiting power 7,8μW

17. Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Future plans Algorithm qualification with IR laser and 3 H Amersham standards Algorithm qualification with IR laser and 3 H Amersham standards Pedestal and noise update implementation Pedestal and noise update implementation Hot pixels on-line masking implementation Hot pixels on-line masking implementation Test beam – Mimosa 5 as a DUT Test beam – Mimosa 5 as a DUT