1. Volker Lindenstruth (www.ti.uni-hd.de) Kirchhoff Institute for Physics Chair of Computer Science University Heidelberg, Germany Phone: +49 6221 54 4303 Fax:+49 6221 54 4345 Email:ti@kip.uni-heidelberg.deti@kip.uni-heidelberg.de WWW:www.ti.uni-hd.de HLT RORC

2. Volker Lindenstruth (www.ti.uni-hd.de) 2 The logical HLT RORC

3. Volker Lindenstruth (www.ti.uni-hd.de) 3 HLT RORC Requirements Operable in two modes –DAQ-only (Backward compatibility with pRORC) –HLT mode (Mode B1/B2) Permanent (beyond power cycle) Reconfiguration in situ (without requiring download cable, etc) PCI 66/64 functionality: –master/slave –Bursts –Interrupts –No Cache support –No LOCK transactions (either master nor slave) Universal Card operating in 3.3V and 5V environment (5V may not be essential on the long run) Support different FPGA sizes with same foot print, enabling low- cost version Additional HLT functionality optional by not equipping components Compatible with DDL DIU Any other requirements to be added here ??

4. Volker Lindenstruth (www.ti.uni-hd.de) 4 FPGA Footprint APEX 20KE series Legend (Baseline EP20K200) 672-Pin Fineline BGA Red- Not Connected pins in (available in EP20K400E) Black- Not Connected pins (available in EP20K600E) Blue- Power Pins (VCC INT or VCC IO or GND) Rectangular Black- Dedicated (not available as user I/O) pins Bright Green- Fast I/Os Dark Green- Primary PCI Gray- user I/O / LVDS Rx/Tx Gray grid- user I/O required for configuration Yellow- dedicated clock pins – cannot be used for user I/O

5. Volker Lindenstruth (www.ti.uni-hd.de) 5 HLT RORC Architecture APEX 20KE 200... 1500 FPGA (672 FBGA) PCI 66 MHz 64-Bits 90 I/O SDRAM SODIMM Socket Min. 128 MB;  66 MHz, 64-Bits NIOS Excalibur Periphery CPLD connected to µC bus (Sync)SRAM  4 MB;  66 MHz, D64 BusyNet 10 MHz Boot Flash 2 MB; D8 FLASH 8 MB; D32 D32+A22+C5 SRAM 16 MB; D32(SRAM) CMC‘ JN3/4 Mezz Conn JN2A 10BT Ethernet connected to µC bus ADC/DAC USB Version SerFlash CAN SerPorts OptoCoupler Power Management LVDS Rx/Tx Miscellaneous Periphery (shared with JN6/CPLD) Mezz Conn JN5 CMC (S/DIU) JN1/2

6. Volker Lindenstruth (www.ti.uni-hd.de) 6 The Real Thing Front side

7. Volker Lindenstruth (www.ti.uni-hd.de) 7 The Real Thing solder side

8. Volker Lindenstruth (www.ti.uni-hd.de) 8 Some Performance

9. Volker Lindenstruth (www.ti.uni-hd.de) 9 HLT Derandomizing Buffer D32 SRAM Shared Address Individual ALE DIU (D32 / 100 MB/sec) D64 SDRAM Buffer RAM Interface (D64 – 66 MHz / 528 MB/sec) D64, 66 MHz bursts PCI Core Incl. DMA D64, 66 MHz bursts (max 256 Bte) HLT FPGA Coprocessor ARB Inside APEX

10. Volker Lindenstruth (www.ti.uni-hd.de) 10 Mother Board Layout Sketch JN1JN2 JN4 JN3 JN2A APEX SRAM SDRAM Power (1.8V Gen.) CIAmiscellaneous Connectors JN5 Flash SRAM No

11. Volker Lindenstruth (www.ti.uni-hd.de) 11 RORC with Mezzanine Cards