1. BPM System Status P. Cameron 13 Aug 07

2. Outline 1.Notes from NSLS-II Design Review (last Thursday) 2.System Block Diagram 3.Process Variables 4.DAQ status 5.PUE status 6.Meeting plans

4. Notes from NSLS-II Design Review Committee members: Marc Ross (FNAL), B.X. Yang (APS), Om Singh (APS/NSLS-II), Gunther Rehm (Diamond), Bob Hettel (SLAC) 1.Bergoz in-flange transformers have epoxy vacuum breaks, they leak, use BPM sum signal instead 2.Button design looks good, may be concern with trapped modes with high current (>100mA) and short bunches (<15psec rms) 3.Considerable discussion of Libera - presently this is NSLS-II baseline, driven by manpower, crossbar and feedbacks 4.Libera has required extensive local support from existing users (several man years at Diamond), ‘plug and play’ perception may not be realistic 5.DESY is exploring Xilinx demo board approach as Libera alternative, we are contacting them 6.At Diamond all orbit feedbacks, both slow (~0.1Hz) and fast (~100Hz) are implemented with reflected memory, no real-time EPICS involve

5. Suggestions for upcoming meeting agendas July 30 th – AP presentation/discussion on beam and machine modes, global naming convention, MPS reqt’s for commissioning Aug 6 th – joint AP/Diagnostics discussion on Process Variables, Diagnostics Prioritization (AP shifted emphasis to ‘system status’ discussions) Aug 13 th - Scraper/Collimator Aug 20 th – presentation and discussion of BPM status Aug 27 th – presentation and discussion of BLM status Sep 10 th – presentation and discussion of DCCT and differential current status Sep 17 th – presentation and discussion of Profile status Sep 24 th, Oct 1 st – ???? Oct 8 th – Preparation for Design Review Oct 15 th – Design Review –Committee members – at least 2 from NSLSII, maybe more? Promote collaboration with those guys –Igor Pinayev, Om Singh, Bob Dalesio, else??? Sequence???

6. BPM (also FCT, DCCT, BLM,…) Block Diagram

7. threshold?

8. BPM DAQ Status Two approaches under consideration: COTS Xilinx demo board We understand how to interface this board to timing and controls systems, and provide for 1 sec and abort PVs Presently available hardware requires design and fab of digitizer mezzanine (not an issue, but…) Negotiating with vendors regarding design and release of complete BPM board as demo board As suggested by review committee, discussing with DESY Presently running for Differential Current Libera Not clear how to interface this box to timing and controls systems, and provide for 1 sec and abort PVs. Hopefully this will be clarified by demo box Demo box due in at the end of the month FPGA source code (~1GB!!!) downloaded, uses old (>2 years) Xilinx tools and Linux

9. BPM PUE Status Buttons are in house (qty 70, 64 required presently) 4 installed on BPM block, leak-checked, measured (S- parameters, DC resistance, capacitance,…), baked to 150C (cert to 200C, known problems with all vendors at 250C), re-measured Remainder are awaiting tech time for testing and sorting Cables – RG-223 order soon? HOM probes Installed in 5 cell cavity transitions ‘soon’ (plating problem) Cables? LMR-195? BTF – use buttons (buy broadband ~5W RF amplifier?)

10. Suggestions for upcoming meeting agendas July 30 th – AP presentation/discussion on beam and machine modes, global naming convention, MPS reqt’s for commissioning Aug 6 th – joint AP/Diagnostics discussion on Process Variables, Diagnostics Prioritization (AP shifted emphasis to ‘system status’ discussions) Aug 13 th - Scraper/Collimator Aug 20 th – presentation and discussion of BPM status Aug 27 th – presentation and discussion of BLM status Sep 10 th – presentation and discussion of DCCT and differential current status Sep 17 th – presentation and discussion of Profile status Sep 24 th, Oct 1 st – ???? Oct 8 th – Preparation for Design Review Oct 15 th – Design Review –Committee members – at least 2 from NSLSII, maybe more? Promote collaboration with those guys –Igor Pinayev, Om Singh, Bob Dalesio, else??? Sequence???