0. High Frequency Behavioral Modeling of Second-Order ΣΔ ModulatorsBy
George Suárez Martínez
Submitted in partial fulfillment of the requirements
for the degree of
MASTERS OF SCIENCE in
Electrical Engineering
February 28, 2006

1. Presentation Outline Motivation Objectives
Second-order Multi-bit ΣΔ Modulator (ΣΔΜ)
Non-idealities
Jitter Noise
Thermal Noise
Capacitance mismatch
Individual Level Averaging (ILA)
Switched-capacitor (SC) integrator
Results
Conclusions

2. Motivation
ΣΔ modulators (ΣΔMs) form part of the core of many today’s mixed-signal designs as cornerstone components of oversampled ΣΔ data converters
ΣΔ converters have become a promising candidate for high-speed, high-resolution, and low-power mixed-signal interfaces
Transistor-level simulation is the most accurate approach (e.g. SPICE)
Impractical for complex systems, long simulation time… can take more than a day for a single case!

3. Motivation Alternate modeling techniques,
Finite-difference equations (z-transform)
Macromodels
Behavioral models
Accurate models are needed for low-power, high speed applications (e.g. GSM and WCDMA)
C,C++ and MATLAB are widely used for behavioral modeling
VHDL-Analog and Mixed Signal (VHDL-AMS) becomes practical, due mixed-signal nature of ΣΔM

4. Objectives
Develop an accurate behavioral model of a high-speed second-order multi-bit ΣΔΜ
Use VHDL-AMS as the modeling language
Develop modular and reusable models for other topologies of ΣΔΜs
Validate the model with SPICE simulations
Validate the model with experimental data for target bandwidths of GSM (200kHz) and WCDMA (2.0 MHz)

5. Second-Order ΣΔΜ (Ideal Model)
First Integrator
Second Integrator + +
0.5 + + 1 + + - -
5-level quantizer
0.5 1
DAC
0.5
Quantization noise
Lack of non-idealities
Jitter Noise
Thermal Noise
Capacitance mismatch
Integrator Dynamics

6. Noise Sources - Jitter Noise
Non-uniform sampling.
For a sine wave the error can be approximated by,
Assumed to be white, Gaussian noise δ Δv

7. Noise Sources - Thermal Noise
Caused by the random motion of electrons due to thermal energy
For switched-capacitor ΣΔΜs thermal noise is due the integrator:
switches resistance
operational transconductance amplifier (OTA)
Based on track and hold operation of switched- capacitor (SC) systems

8. Noise Sources - Thermal Noise
Sampling
Integration

9. Capacitance Mismatch Integrator gains are built using capacitor ratios
In multibit architectures DAC mismatch introduces harmonic distortion
Dynamic Element Matching (DEM) such as Individual Level Averaging (ILA) is employed
0.5 +
First Integrator 1
Second Integrator
quantizer
DAC

10. Individual Level Averaging (ILA)
Internal DAC unitary model
DAC
din
unit2
unit1
Thermometer
decoder +
vout 2
ILA algorithm transfer curves
ideal
“00”
“01”
“10”
0.5
1.0
din
vout
0.5
1.0
“00”
“01”
“10”
unit1
din
vout
“00”
“01”
“10”
0.5
1.0
unit2
din
vout
Error due
mismatch
Example
ideal
0.25
0.5
vout
unit1
unit2
“00”
“01”
din
ILA on
0.25
0.5
“00”
“01”
vout
din

11. Integrator Dynamics Fundamental block of ΣΔ Μodulators
Dynamic behavior is the most limiting factor
Limited DC gain
Limited bandwidth
Slew rate limitations
Parasitic capacitances
Capacitive Loads

12. Integrator Dynamic Behavior
Possible cases in SC integrator transient response:
Linear |va| # Io/gm
Partial Slew |va| > Io/gm and t $ to
Slew |va| > Io/gm and t < to
va , SR and to
determine the case
Slew
Linear va SR
OTA input voltage vo
gm(va+-va-) go Co
va+
va-
+Io
-Io to
time

13. SC integrator transient equations
Linear
Slew
Partial Slew

14. SC integrator Flowchart
Yes No
Linear?
start
Slew?
Yes No
Calculate
linear
Read
Calculate
slew
Calculate
partial slew
Calculate
Calculate
*Same flowchart for sampling
and integration phases
end

15. Simulation Results - Model vs SPICE
gm=1.16 mA/V and T=27oC.
Bandwidth
SPICE SNDR
Model SNDR
Error (%)
135kHz
86.56 dB
85.43 dB
1.31
270kHz
74.65 dB
70.35 dB
5.76
615kHz
54.99 dB
51.42 dB
6.50
gm=1.75 mA/V and T=27oC.
Bandwidth
SPICE SNDR
New Model SNDR
Error (%)
135kHz
86.10 dB
84.63 dB
1.71
270kHz
72.45 dB
70.30 dB
2.96
615kHz
53.62 dB
51.34 dB
4.25

16. Simulation Results - Model vs SPICE
gm=1.9 mA/V and T=-30oC.
Bandwidth
SPICE SNDR
New Model SNDR
Error (%)
135kHz
89.90 dB
84.07 dB
6.48
270kHz
71.08 dB
71.04 dB
0.06
615kHz
53.53 dB
51.93 dB
2.99
gm=1. 9 mA/V and T=27oC.
Bandwidth
SPICE SNDR
New Model SNDR
Error (%)
135kHz
87.57 dB
84.98 dB
2.95
270kHz
72.73 dB
70.54 dB
3.01
615kHz
53.37 dB
51.89 dB
2.78

17. Simulation Results for GSM
VHDL-AMS dB
Actual data dB
2.78% error

18. Simulation Results for WCDMA
VHDL-AMS dB
Actual data dB
2.41% error

19. Results-Capacitance Mismatch
DAC mismatch
0.0%
0.1%
1.0%
SNDR (dB)
73.15
57.80
38.00
Individual Level Averaging off

20. Results-Capacitance Mismatch
DAC mismatch
0.0%
0.1%
1.0%
SNDR (dB)
73.15
70.40
51.19
Individual Level Averaging on

21. Results-Thermal Noise
Temperature
-30oC
27oC
100oC

22. Results-Thermal Noise
Capacitor sizes 1X 2X 4X

23. Results-Jitter Noise Jitter models Sampling deviation 70.7128 dB
Derivative dB
0.4 % relative
difference

24. Results-Jitter Noise Jitter standard deviations Input of 62 kHz 0.0 ns

25. Results-Jitter Noise Jitter standard deviations Input of 120 kHz

26. Comparison with Previous Models
Low power case
Smaller Io
Smaller DC gain
Inclusion of go
Traditional Model
Presented Model
Admittance Matrix

27. Admittance Matrix Model VHDL-AMS Transient Model
Speed*
Cycles
Admittance Matrix Model
VHDL-AMS Transient Model
8192
31 min 42 sec
15 sec
16384
1 hr 4 min 42 sec
30 sec
32768
2 hr 12 min 8 sec
1 min
65536
4 hr 13 min 5 sec
2 min 11 sec
A robust algorithmic-level time complexity analysis is difficult!
*Simulations were carried on a Pentium 4 PC with 2GB memory running at 3.0GHz.

28. Conclusions
An accurate model of a second-order multi-bit ΣΔΜ was developed
Addresses several non-idealities such as:
Jitter Noise
Thermal Noise
Capacitance Mismatch
Integrator dynamics
The integrator model an improved behavioral characterization of the degrading effects of settling errors on high-speed ΣΔΜs

29. Conclusions Results against SPICE simulations show errors less than 7%
Results for GSM (200kHz) show 2.78% of error
Results for WCDMA (2.0 MHz) show 2.41% of error in comparison with ≥ 15% for the previous model
Behavioral modeling and simulation with VHDL-AMS is a viable solution to the extensive transistor-level simulation of ΣΔΜs

30. References
J. C. Candy and G. C. Temes. “Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation”. IEEE Press, 1992.
Norsworthy, S. R. and Schreirer, R. and Temes, G. C. “Delta-Sigma Data Converters: Theory Design and Simulation”. IEEE Press, 1997.
G. Gomez and B. Haroun. “A 1.5 V 2.4/2.9 mW 79/50 dB DR SD modulator for GSM-WCDMA in a 0.13 µm digital process”. ISSCC, pages 467–469, 2002.
Medeiro, F. and Perez-Verdu, A. and Rodriguez-Vazquez, A. “Top-Down Design of High-Performance Sigma-Delta Modulators”. Kluwer Academic Publishers, 1999.
Sansen, W. Transient Analysis of Charge Transfer in SC Filters: Gain and Error Distortion. IEEE Journal of Solid State Circuits, 22:268–276, 1987.
F.O. Fernandez and M. Jimenez. “Behavioral Modeling of Dynamic Capacitive Loads on Sigma-Delta Modulators”. Seminario Anual de Automatica Electronica Industrial e Instrumentacion, 1:119–122, 2002.
G. Suarez and M. Jimenez. “Behavioral Modeling of Sigma Delta Modulators using VHDL-AMS”. IEEE Midwest Symposium on Circuits and Systems, 2005.
G. Suarez, M. Jimenez and F. Fernandez. “Behavioral Modeling Methods for Switched-Capacitor ΣΔ Modulators”. Submitted to IEEE Transactions on Circuits and Systems Journal.
G. Suarez and M. Jimenez. “Considerations for Accurate Behavioral Modeling of High-Speed SC ΣΔ Modulators”. Submitted to IEEE International Symposium on Circuits and Systems.

31. Acknowledgements Dr. Manuel Jiménez Dr. Rogelio Palomera
Dr. Domingo Rodríguez
Felix O. Fernández
This work was partially supported by Texas Instruments through the TI-UPRM Program.

32. Questions?