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CASE STUDY OF A MULTYCYCLE DATAPATH
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Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: 1 memory, 1 ALU Ideal Memory Din Address 32 Dout MemWr 32 ALU 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb 5 5 32 busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSrcA Mux 01 RegDst Mux 0 1 32 PC MemtoReg Extend Mux 0 1 32 0 1 2 3 4 16 Imm 32 ALUSrcB Mux 1 0 32 Zero PCWrCondPCSrc 32 IorD Mem Data Reg ALU Out B A << 2 MemRd PC
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State Diagram: operations for Each Cycle R-Type IR Mem[PC] State= 00000 A R[rs] B R[rt] PC PC + 4 State= 00001 ALUout A Op B State= 01000 R[rd] ALUout State= 01001 Go Next state= 00000 Logic Immediate IR Mem[PC] State= 00000 A R[rs] B R[rt] PC PC + 4 State= 00010 ALUout A Op ZeroExt[imm16] State= 01010 R[rt] ALUout State= 01011 Go Next state= 00000 Load IR Mem[PC] State= 00000 A R[rs] B R[rt] PC PC + 4 State= 00011 ALUout A Op SignExt[imm16] State= 01100 MDR ALUout State= 01101 R[rt] MDR State= 01110 Go Next state= 00000 Store IR Mem[PC] State= 00000 A R[rs] B R[rt] PC PC + 4 State= 00100 ALUout A Op SignExt[imm16] State= 01111 Mem[R] ALUout State= 010000 Go Next state= 00000 Cond-Branch IR Mem[PC] State= 00000 A R[rs], B R[rt], Z[R[rs]-R[rt]] PC PC + 4 State= 00101 PC (PC + 4) + (Z=1) (SignExt(imm16) x4) State= 010001 Go Next state= 00000 IF ID EX/M WB Branch IR Mem[PC] State=00000 PC [PC + 4] 28-31, (IMM-26) 26 ] State= 00110 Go Next State 00000
![State Diagram: operations for Each Cycle R-Type IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op B State= R[rd] ALUout State= Go Next state= Logic Immediate IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op ZeroExt[imm16] State= R[rt] ALUout State= Go Next state= Load IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op SignExt[imm16] State= MDR ALUout State= R[rt] MDR State= Go Next state= Store IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op SignExt[imm16] State= Mem[R] ALUout State= Go Next state= Cond-Branch IR Mem[PC] State= A R[rs], B R[rt], Z[R[rs]-R[rt]] PC PC + 4 State= PC (PC + 4) + (Z=1) (SignExt(imm16) x4) State= Go Next state= IF ID EX/M WB Branch IR Mem[PC] State=00000 PC [PC + 4] 28-31, (IMM-26) 26 ] State= Go Next State 00000](http://images.slideplayer.com/25/8057236/slides/slide_3.jpg "State Diagram: operations for Each Cycle R-Type IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op B State= R[rd] ALUout State= Go Next state= Logic Immediate IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op ZeroExt[imm16] State= R[rt] ALUout State= Go Next state= Load IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op SignExt[imm16] State= MDR ALUout State= R[rt] MDR State= Go Next state= Store IR Mem[PC] State= A R[rs] B R[rt] PC PC + 4 State= ALUout A Op SignExt[imm16] State= Mem[R] ALUout State= Go Next state= Cond-Branch IR Mem[PC] State= A R[rs], B R[rt], Z[R[rs]-R[rt]] PC PC + 4 State= PC (PC + 4) + (Z=1) (SignExt(imm16) x4) State= Go Next state= IF ID EX/M WB Branch IR Mem[PC] State=00000 PC [PC + 4] 28-31, (IMM-26) 26 ] State= Go Next State 00000")
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Current Op fieldZNext IR PC Ops Exec Mem Write-Back State A B Ex Sr ALU S R W MM-R Wr Dst R I LW SW BEQ IF ID
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Current Op fieldZNext IR PC Ops Exec Mem Write-Back State A B Ex Sr ALU S R W MM-R Wr Dst 00000XXXX?000011 00001R-typex010001 1 00010I-typex010101 1 00011 LWx01100 1 1 00100SWx01111 1 1 00101BEQ x001111 1 00110 Jumpx000001 1 00111 xxxxxxx000001 1 01000xxxxxxx01001 0 1 fun 1 01001xxxxxxx000001 0 0 1 1 01010xxxxxxx01011 0 0 or 1 01011xxxxxxx000001 0 0 1 0 01100xxxxxxx01101 1 0 add 1 01101xxxxxxx01110 1 0 1 01110xxxxxxx000001 0 1 1 0 01111xxxxxxx100001 0 add 1 10000xxxxxxx00000 1 00 1 R I LW SW BEQ IF ID
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