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Page 1 Workshop for Electron Beam Lithography System JBX-6300FS By Nelson LI 13 November 2009 Nanoelectronics Fabrication Facility.

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Presentation on theme: "Page 1 Workshop for Electron Beam Lithography System JBX-6300FS By Nelson LI 13 November 2009 Nanoelectronics Fabrication Facility."— Presentation transcript:

1 Page 1 Workshop for Electron Beam Lithography System JBX-6300FS By Nelson LI 13 November 2009 Nanoelectronics Fabrication Facility

2 Page 2 1.System specifications 2.Importance of chip feature on writing result 3.Requirements of overlay writing 4.Photoresist provide 5.Requirements of pattern design 6.Exposure result 7.Charging scheme

3 Page 3 1.System specifications System model Basic specifications Substrates supported by system

4 Page 4 System specifications Manufacturer: JEOL Model No: JBX-6300FS SYSTEM MODEL

5 Page 5 System specification Specifications Writing modeHigh speed or high precision Beam Current30pA to 20nA Scanning Speed12M to 250 Hz Accelerate Voltage 20, 50 or 100 kV Max. Field Size (um 2 ) High speed mode: 2000 (20kV), 1000(50kV) or 500 (100kV) High precision mode: 250 (20kV), 125(50kV) or 62.5 (100kV) BASIC SPECIFICATIONS

6 Page 6 System specifications SUBSTRATES SUPPORTED BY SYSTEM SubstratesSize Mask5”x5”x0.09” Wafer4”, 3” or 2” Nano-imprint mask65mm x 65mm x 6.35mm Chip sample2cm x 2cm, 1.5cm x 1.5cm or 1cm x 1cm

7 Page 7 2.Importance of chip feature on writing result Cassette to mount chip Cases of improper chip feature i, chip with rough edge ii, chip with incorrect size Requirements of chip feature

8 Page 8 Importance of chip feature on writing result Cassette to mount chip: Picture of cassette Back of cassetteFront of cassette (writing side) Grounding pins Positioning pins Chip backside Chip surface with PR Exposure window

9 Page 9 Cases of improper chip feature Chip with rough edges Cassette backCassette front (writing side) Problem:i, Grounding pin cannot touch on sample surface ii, May cause rotation error

10 Page 10 Cases of improper chip feature Chip with incorrect size Cassette back (for 15mm x15mm) chip) Cassette front (writing side) Problem:Exposure area shift from center of chip Exposure window 18mm x 18mm chip Exposure window Exposure window center Chip center

11 Page 11 Importance of chip feature on writing result Requirements of chip feature Straight and smooth cutting edge Square shape with orthogonal angles For overlay writing, patterns of previous layer should be located at the center of chip

12 Page 12 3.Requirements of overlay writing Feature of Global and Chip alignment marks Positions of Global and Chip alignment marks

13 Page 13 Requirements of overlay writing Feature of Global and Chip alignment marks L W Global Mark:L= 1500 μm W = 3 μm Chip Mark:L= 20 μm W = 3 μm Etch depth of Mark: ≧ 1 μm

14 Page 14 Positions of Global alignment marks on wafer L Requirements of overlay writing Wafer For 4” wafer, L ≦ 40.5mm For 2” wafer, L ≦ 19mm

15 Page 15 Requirements of overlay writing Positions of Chip alignment marks on wafer Four chip alignment marks located at 4 corners of writing chip M1, M2, M3 and M4 respectively.

16 Page 16 4.Photoresist Provide Positive photoresist i,ZEP-520A (thickness ~ 400 to 100nm) ii,ZEP-7000 (for mask, thickness ~ 400 to 150nm) iii,PMMA950-A2 (thickness ~ 180 to 80nm) Negative photoresist i,AR-N7520.18 (thickness ~ 400nm) ii,AR-N7520.073 (thickness ~ 100nm)

17 Page 17 5.Requirements of pattern design File format, pattern sizes and pattern area Pattern samples

18 Page 18 Requirements of pattern Pattern sizes and file format File format:GDSII Total number of vertex point per polygon ≦ 600 Pattern sizes(line width or gap size) ≧ 100nm Pattern Complexity ↑, file conversion time ↑

19 Page 19 Requirements of pattern Pattern sizes and file format Problems of larger exposure area i,long writing time ii,high risk of field stitching error due to laboratory temperature fluctuation Stitching error

20 Page 19 Requirements of pattern Pattern sizes and file format iii,Proximity error Correct expose Over expose 100 μm 120 μm

21 Page 20 Requirements of pattern Pattern sample 1 1500 μm Chip area:1500um 2 Exposure area:11.51% of Chip area Exposure time:10.4mins

22 Page 21 Requirements of pattern Pattern sample 2 500 μm Chip area:500um 2 Exposure area:11.51% of Chip area Exposure time:1min 0.2 μm line width

23 Page 22 Requirements of pattern Pattern sample 3 500 μm Pattern conversion fail! 0.1 μm x 0.2 μm polygon 100 μm

24 Page 23 6.Exposure result Pattern sample 1 Pattern sample 2

25 Page 24 Exposure result Pattern sample 1:Shot bar pattern ZEP-520A (+)ma-N2403 (-) 80nm line width 100nm line width

26 Page 25 Exposure result Pattern sample 1 ZEP-520A (+)ma-N2403 (-) 100nm line width 100nm 2 square pattern

27 Page 26 Exposure result Pattern sample 1 50nm line patterns with 0.3 ° rotation angleZigzag patterns with 100nm line width ZEP-520A (+)

28 Page 27 Exposure result Pattern sample 2 ZEP-520A (+)ma-N2403 (-)

29 Page 28 7.Charging Scheme Definitions of Short and Long jobs Charging for internal users Charging for other HK Institutions Charging for external users Job submission procedure

30 Page 29 Charging Scheme Charging Scheme : Definition of Short and Long jobs Short job:Exposure time ≦ 3hrs Long job:Exposure time ﹥ 3hrs

31 Page 30 Long Job(HK$)Short Job(HK$) 5”x5” soda lime mask22441494 5”x5” quartz mask28142064 Wafer or chip sample22321482 Nano-imprint mask27461996 Charging Scheme : Charging for internal users Charging Scheme

32 Page 31 Other HK InstitutionsExternal Users Long Job(HK$)Short Job(HK$)Long Job(HK$)Short Job(HK$) 5”x5” soda lime mask 50744204113767355 5”x5” quartz mask 57354865120378016 Wafer or chip sample 50604190113627341 Nano-imprint mask 812772571442910408 Charging Scheme : Charging for external users and other HK Institutions Charging Scheme Remark: Price includes 16% administration fee

33 Page 32 Job submission procedure: internal users Charging Scheme The price list of substrates will post on website on coming Monday!

34 Page33 1.Go to www.nff.ust.hk 2. 3. Charging Scheme Job submission procedure: for external users and other HK Institutions 4.

35 Page 34 Job submission procedure Contact Information : Name: Nelson LI Email : eenelson@ust.hk Thankyou Nanoelectronics Fabrication Facility


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